Rxdisperr; Rxnotintable; Vitesse Disparity Example; Transmitting Vitesse Channel Bonding Sequence - Xilinx RocketIO User Manual

8B/10B Encoding/Decoding
The RXRUNDISP port indicates the disparity of the received byte is either negative or positive.
RXRUNDISP asserted High indicates positive disparity. This is used in cases like the
Disparity Example"
asserted to flag the presence of an inserted clock correction sequence.
In the bypassed configuration, RXCHARISK and RXRUNDISP are additional data bits for the 10-
, 20-, or 40-bit buses, similar to the configuration on the transmit side. RXCHARISK [0:3] relates to
bits 9, 19, 29, and 39, while RXRUNDISP pertains to bits 8, 18, 28, and 38 of the data bus. See
Figure

RXDISPERR

RXDISPERR is a status port for the receiver that is byte-mapped to RXDATA. When a bit in
RXDISPERR is asserted High, it means that a disparity error has occurred in the received data. This
usually indicates data corruption (bit errors) or transmission of an invalid control character. It can
also occur in cases where normal disparity is not required, such as in the
Example".

RXNOTINTABLE

RXNOTINTABLE is a status port for the receiver that is byte-mapped to RXDATA. When it is
asserted High, it means that the received data is not in the 8B/10B tables. This port is only used
when the 8B/10B decoder is enabled.

Vitesse Disparity Example

To support other protocols, the transceiver can affect the disparity mode of the serial data
transmitted. For example, Vitesse channel-to-channel alignment protocol sends out:
instead of:
The logic must assert TXCHARDISPVAL to cause the serial data to send out two negative running
disparity characters.

Transmitting Vitesse Channel Bonding Sequence

The RocketIO core receives this data, but for cases where TXCHARDISPVAL is set High during
data transmission, the disp_err bit in CHAN_BOND_SEQ must also be set High.
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
below. When CLK_COR_INSERT_IDLE_FLAG = TRUE, RXRUNDISP is
2-14.
K28.5+ K28.5+ K28.5- K28.5- or K28.5- K28.5- K28.5+ K28.5+
K28.5+ K28.5- K28.5+ K28.5- or K28.5- K28.5+ K28.5- K28.5+
Note:
If bypassing 8B/10B encoding/decoding, the remaining 10 bits will be the 10-bit-encoded
version of the channel bonding sequence. This is the same as the clock correction sequence
shown in Table 2-15, page 75.
TXBYPASS8B10B
| TXCHARISK
| | TXCHARDISPMODE
| | | TXCHARDISPVAL
| | | | TXDATA
| | | | |
0 1 0 0 10111100
0 1 0 1 10111100
0 1 0 0 10111100
0 1 0 1 10111100
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K28.5+ (or K28.5-)
K28.5+ (or K28.5-)
K28.5- (or K28.5+)
K28.5- (or K28.5+)
R
"Vitesse
"Vitesse Disparity
65