Running The Gtx Ibert Demonstration - Xilinx Virtex-7 FPGA VC7203 Getting Started Manual

Running the GTX IBERT Demonstration

The GTX IBERT demonstration operates one GTX Quad at a time. This section describes how
to test GTX Quad 115. The remaining GTX Quads are tested following a similar series of
steps.
Connecting the GTX Transceivers and Reference Clocks
Figure 1-1 shows the locations for GTX transceiver Quads 113, 114, 115, 116, 117, 118, and
119 on the VC7203 board.
Figure 1-1
Note:
X-Ref Target - Figure 1-1
All GTX transceiver pins and reference clock pins are routed from the FPGA to a connector
pad which interfaces with Samtec BullsEye connectors.
pad. Figure 1-2
VC7203 IBERT Getting Started Guide
UG847 (Vivado Design Suite v2015.1) April 27, 2015
is for reference only and might not reflect the current revision of the board.
Figure 1-1: GTX Quad Locations
B shows the connector pinout.
www.xilinx.com
Chapter 1: VC7203 IBERT Getting Started Guide
Figure 1-2 A shows the connector
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