Encoder; Table 2-5: Running Disparity Control - Xilinx RocketIO X User Manual

R

Encoder

A bypassable 8B/10B encoder is included in the transmitter. The encoder uses the same
256 data characters and 12 control characters (shown in
Characters") that are used for Gigabit Ethernet, XAUI, Fibre Channel, and InfiniBand.
The encoder accepts 8 bits of data along with a K-character signal for a total of 9 bits per
character applied. If the K-character signal is High, the data is encoded into one of the 12
possible K-characters available in the 8B/10B code. If the K-character input is Low, the
8 bits are encoded as standard data.
There are two ports that enable the 8B/10B encoding in the transceiver. The
TXBYPASS8B10B is a byte-mapped port that is 1, 2, 4 or 8 bits depending on the data width
of the transceiver primitive being used. These bits correlate to each byte of the data path.
To enable the 8B/10B encoding of the transmitter, these bits should be set to a logic 0. In
this mode, the transmit data that is input to the TXDATA port is non-encoded data of either
8, 16, 32, or 64 bits wide. However, if other encoding schemes are preferred, the encoder
capabilities are bypassed by setting all bits to a logic 1. The extra bits are fed through the
TXCHARDISPMODE and TXCHARDISPVAL buses.
TXCHARDISPVAL and TXCHARDISPMODE
TXCHARDISPVAL and TXCHARDISPMODE are dual-purpose ports for the transmitter
depending whether 8B/10B encoding is done.
When encoding is enabled, these ports function as byte-mapped control ports controlling
the running disparity of the transmitted serial data

Table 2-5: Running Disparity Control

In the encoding configuration, the disparity of the serial transmission can be controlled
with the TXCHARDISPVAL and TXCHARDISPMODE ports. When TXCHARDISPMODE
is set to a logic 1, the running disparity is set before encoding the specific byte.
TXCHARDISPVAL determines if the disparity is negative (set to a logic 0) or positive (set
to a logic 1).
When TXCHARDSIPMODE is set to a logic 0, the running disparity is maintained if
TXCHARDISPVAL is also set to a logic 0. However, the disparity is inverted before
encoding the byte when the TXCHARDISPVAL is set to a logic 1.
Most applications use the mode where both TXCHARDISPMODE and TXCHARDISPVAL
are set to logic 0. Some applications can use other settings if special running disparity
configurations are required, such as in the
In the bypassed configuration, TXCHARDISPMODE[0] becomes bit 9 of the 10 bits of
encoded data (TXCHARDISPMODE[1:7] are bits 19, 29, 39, 49, 59, 69, and 79 in the 20-bit
and 40-bit and 80-bit wide buses). TXCHARDISPVAL becomes bits 8, 18, 28, 38, 48, 58, 68,
and 78 of the transmit data bus while the TXDATA bus completes the bus. See
48
{txchardispmode,
txchardispval}
00 Maintain running disparity normally
01 Invert normally generated running disparity before
encoding this byte
10 Set negative running disparity before encoding this byte
11 Set positive running disparity before encoding this byte
Chapter 2: Digital Design Considerations
Table 2-6
Function
"Vitesse Disparity Example," page
www.xilinx.com
1-800-255-7778
Appendix B, "8B/10B Valid
shows this dual functionality.
(Table 2-5).
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
52.
Table 2-6.