Mgt Package Pins; Table 5-1: Loc Grid And Package Pins Correlation For Ff896Package; Table 5-2: Loc Grid And Package Pins Correlation For Ff1704 Packages - Xilinx RocketIO X User Manual

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MGT Package Pins

The MGTs make up a hard core placed in the FPGA fabric; all package pins for the MGTs
are dedicated on the Virtex-II Pro X device. This is shown in the package pin diagrams in
the Virtex-II Pro data sheet. When creating a design, LOC constraints must be used to
implement a specific MGT on the die. This LOC constraint also determines which package
pins are used.
package pins themselves. The pin numbers are the TXNPAD, TXPPAD, RXPPAD, and
RXNPAD, respectively. The power pins are adjacent to these pins in the package pin
diagrams of the handbook.

Table 5-1: LOC Grid and Package Pins Correlation for FF896Package

Table 5-2: LOC Grid and Package Pins Correlation for FF1704 Packages

126
Table 5-1 and
LOC Constraints
GT_X0_Y0
GT_X0_Y1
GT_X1_Y0
GT_X1_Y1
GT_X2_Y0
GT_X2_Y1
GT_X3_Y0
GT_X3_Y1
LOC Constraints
GT_X0_Y0
GT_X0_Y1
GT_X1_Y0
GT_X1_Y1
GT_X2_Y0
GT_X2_Y1
GT_X3_Y0
GT_X3_Y1
GT_X4_Y0
GT_X4_Y1
GT_X5_Y0
GT_X5_Y1
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Chapter 5: Simulation and Implementation
Table 5-2 show the correlation between the LOC grid and the
FF896
XC2VPX20
AK27, AK26, AK25, AK24
A27, A26, A25, A24
AK20, AK19, AK18, AK17
A20, A19, A18, A17
AK14, AK13, AK12, AK11
A14, A13, A12, A11
AK7, AK6, AK5, AK4
A7, A6, A5, A4
FF1704
XC2VPX70
BB41, BB40, BB39, BB38
A41, A40, A39, A38
BB37, BB36, BB35, BB34
A37, A36, A35, A34
BB33, BB32, BB31, BB30
A33, A32, A31, A30
BB29, BB28, BB27, BB26
A29, A28, A27, A26
BB25, BB24, BB23, BB22
A25, A24, A23, A22
BB21, BB20, BB19, BB18
A21, A20, A19, A18
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004