Mgt Package Pins - Xilinx RocketIO User Manual

Product Not Recommended for New Designs

MGT Package Pins

MGT Package Pins
The MGT is a hard core placed in the FPGA fabric; all package pins for the MGTs are
dedicated on the Virtex-II Pro device. This is shown in the package pin diagrams in the
Virtex-II Pro Platform FPGA User
used to implement a specific MGT on the die. This LOC constraint also determines which
package pins are used.
package pins themselves. The pin numbers are TXNPAD, TXPPAD, RXPPAD, and
RXNPAD, respectively. The power pins are adjacent to these pins in the package pin
diagrams of the User Guide.
Table 4-1: LOC Grid & Package Pins Correlation for FG256/456 & FF672
Constraints
GT_X0_Y0
GT_X0_Y1
GT_X1_Y0
GT_X1_Y1
GT_X2_Y0
GT_X2_Y1
GT_X3_Y0
GT_X3_Y1
RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
Table 4-1
FG256
LOC
2VP2/2VP4
T4, T5, T6, T7 AB7, AB8,
AB9, AB10
A4, A5, A6, A7, A8, A9,
A7 A10
T10, T11, T12, AB13,AB14,
T13 AB15, AB16
A10, A11, A13, A14,
A12, A13 A15, A16
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Guide. When creating a design, LOC constraints must be
shows the correlation between the LOC grid and the
FG456
2VP2/2VP4 2VP7
AB3, AB4,
AB5, AB6
A3, A4, A5,
A6
AB7, AB8,
AB9, AB10
A7, A8, A9,
A10
AB13, AB14,
AB15, AB16
A13, A14,
A15, A16
AB17, AB18,
AB19, AB20
A17, A18,
A19, A20
FF672
2VP2/2VP4 2VP7
AF18, AF17, AF23, AF22,
AF16, AF15 AF21, AF20
A18, A17, A23, A22,
A16, A15 A21, A20
AF12, AF11, AF18, AF17,
AF10, AF9 AF16, AF15
A12, A11, A18, A17,
A10, A9 A16, A15
AF12, AF11,
AF10, AF9
A12, A11,
A10, A9
AF7, AF6,
AF5, AF4
A7, A6, A5,
A4
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