Package Placement Information - Xilinx Virtex-5 RocketIO GTP User Manual

Chapter 4: Implementation

Package Placement Information

The diagrams in this section illustrate GTP_DUAL placement for the following packages:
•
•
Figure 4-1
placement name is the name used in the UCF to map GTP_DUAL tiles instantiated in the
design to specific tiles on the device. The board-level pin names and numbers are the
names placed in the PKG file generated by the ISE design flow. This file is typically used by
board-level schematic capture and layout tools to create component symbols and layout
footprints.
GTP_DUAL
Placement Name
GTP_DUAL_X0Y3
52
LXT packages:
♦
XC5VLX30T-FF665
♦
XC5VLX50T-FF665
♦
XC5VLX50T-FF1136
♦
XC5VLX85T-FF1136
♦
XC5VLX110T-FF1136
♦
XC5VLX110T-FF1738
♦
XC5VLX220T-FF1738
♦
XC5VLX330T-FF1738
SXT packages:
♦
XC5VSX35T-FF665
♦
XC5VSX50T-FF665
♦
XC5VSX50T-FF1136
♦
XC5VSX95T-FF1136
illustrates the nomenclature used in each of these diagrams. The GTP_DUAL
D4
D3
F1
E1
C1
D1
G2
F2
B2
C2
Figure 4-1: Placement Diagram Nomenclature
www.xilinx.com
Board-Level
Pin Names
MGTREFCLKP_116
MGTREFCLKN_116
MGTRXP1_116
MGTRXN1_116
MGTRXP0_116
MGTRXN0_116
MGTTXP1_116
MGTTXN1_116
MGTTXP0_116
MGTTXN0_116
Board-Level
Pin Numbers
Virtex-5 RocketIO GTP Transceiver User Guide
F3 MGTAVCCPLL_116
MGTAVCC_116
E3
E4
MGTAVCC_116
C3 MGTAVTTRX_116
B3 MGTAVTTTX_116
G3 MGTAVTTTX_116
UG196_c4_01_102006
UG196 (v1.3) May 25, 2007
R