Samsung S5PC100 User Manual page 1229

3D-ACCELERATOR
1.2 OVERALL ARCHITECTURE
Overall graphics pipeline consists of one vertex pipeline and two pixel pipelines.
Host
32‐bit
Interface
AHB
(HI)
9.6-2
Post
Primitive
Vertex
Engine
Cache
(PE)
(PVC )
Vertex
Shader
(VS)
Vertex Texture
Unit
Texture
L2
Vertex Texture
Cache
L1 Cache
Figure 9.6- 1 Overall Block
Triangle
Setup Rasterizer
Engine (RA)
(TSE )
Pixel
Shader
(PS)
Pixel
Shader
(PS)
DMA
64‐bit AXI (3‐channel )
Diagram.
S5PC100 USER'S MANUAL (REV1.0)
Per‐
Fragment
(PF)
Per‐
Fragment
(PF)