Dsd Interface; Figure 43: Iec 60958 Sub-Frame Timing Diagram; Figure 44: Aes3 Sub-Frame Timing Diagram; Figure 45: Aes3 Stream Timing Diagram - Analog Devices Advantiv ADV7604 Hardware Manual

0
L
S
B
Channel A
LSB MSB
Frame n

7.16.8 DSD Interface

The ADV7604 incorporates a 6-DSD channel interface used to output the audio stream extracted
from DSD packets. Each of the DSD channels carries an over-sampled 1-bit representation of the
audio signal as delivered on Super Audio CDs (SACDs).
DSD Interface IO
DSD0A
DSD0B
DSD1A
DSD1B
DSD2A
DSD2B
SCLK
MCLKOUT
Rev. F August 2010

Figure 43: IEC 60958 Sub-frame Timing Diagram

Data

Figure 44: AES3 Sub-frame Timing Diagram

U C B
V
32 Clock Slots

Figure 45: AES3 Stream Timing Diagram

Table 18: DSD Interface Description

Function
1
2
3
4
5
6
Bit clock
Audio master clock output
23 24
M
V
S
B
Validity Flag
User Data
Channel Status
Block Start Flag
Channel B
LSB MSB V
U
32 Clock Slots
st
DSD data channel
nd
DSD data channel
rd
DSD data channel
th
DSD data channel
th
DSD data channel
th
DSD data channel
141
27
U C B 0 0 0
Zero Padding
C
B
Frame n + 1
ADV7604
31
0