Evm Digital Inputs And Outputs - Texas Instruments INA260EVM-PDK Instruction Manual

INA260EVM-PDK Hardware

2.3 EVM Digital Inputs and Outputs

The only digital input signals required to operate the INA260 are the 2-bit I
clock (SCL), and serial data (SDA), which is a bidirectional pin and thus also an output. The device address
bits can each assume one of four values: GND, V
summarized in Table 2-2. The values of A0 and A1 must be set using jumpers J2 and J3, respectively.
A1
GND
GND
GND
GND
V
S+
V
S+
V
S+
V
S+
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
The SM-USB-DIG drives the SCL and SDA through the J4 connector socket. These are open-drain inputs
and the EVM contains pullup resistors to drive these inputs high when the corresponding SM-USB-DIG digital
outputs are in tri-state. Both fast (1 kHz to 400 kHz) and high-speed (1 kHz to 2.94 MHz) I
supported.
The outputs of the INA260 include SDA and ALERT, both of which are routed to J4 and are readable from the
GUI. The GUI includes support for both over- and underlimit as well as conversion ready indicator modes of the
ALERT pin. The state of the ALERT pin can be read from either the GUI or the onboard LED indicator.
10 INA260EVM-PDK (Rev A)
, SDA or SCL, resulting in 16 possible target addresses
S
2
Table 2-2. INA260 I C Address Configuration
A0
GND
V
S+
SDA
SCL
GND
V
S+
SDA
SCL
GND
V
S+
SDA
SCL
GND
V
S+
SDA
SCL
Copyright © 2023 Texas Instruments Incorporated
2
C device address (A[1:0]), serial
TARGET ADDRESS
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
2
C modes are
SBOU180A – NOVEMBER 2016 – REVISED MARCH 2023
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