Dmd Reset And Block Clear Signals To The Dlpc910; Dlpc910 Initialization And Controller Reset Signals; Dlpc910 Status-Info Signals; Table 3-3. Reset And Block Clear Signals - Texas Instruments DLPLCRC910EVM User Manual

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Name
ns_flip

3.3 DMD Reset and Block Clear Signals to the DLPC910

Table 3-3 lists the DMD Reset and Block Clear signals to and from the DLPC910. These signals connect through
the VC-707 FMC connectors. Refer to the DLPC910 data sheet for additional information.
Name
blkad(3:0)
blkmd(1:0)
rst2blkz
wdt_enablez
rst_active

3.4 DLPC910 Initialization and Controller Reset Signals

Table 3-4 describes the initialization signals for the DLPC910 controller. See the DLPC910 data sheet for
additional signal information.

Table 3-4. DLPC910 Initialization and Controller Reset Signals

Name
ctrl_rstz
pwr_floatz
ecp2_finished
init_active
3.5 Apps FPGA Reset Signal - apps_resetz
Signal apps_resetz originates from a push button switch (SW1 APP RST) on the DLPLCRC910EVM board.
When the switch is pressed the apps_resetz signal goes low, causing the init-run-park state machine in the
apps FPGA to drive pwr_floatz low to park the DMD mirrors. Upon release of the push button switch, the
init-run-park state machine re-initializes the DLPC910 controller and resets the Apps FPGA logic.

3.6 DLPC910 Status-Info Signals

DLPC910 status-info signals are listed in
from the DLPC910 controller. Only DMD_type is used by the Apps FPGA logic. The version and irq signals are
made available in status registers via the USB GPIF.
The DMD_speed_sel signal is from a set of jumpers on the DLPLCRC910EVM board. The jumper settings are
used by DLPC910 controller and by Apps FPGA to determine clock frequency of the LVDS high speed interface
DLP9000X and DLP9000XUV.
Reference the DLPC910 data sheet for additional information.
Name
ddc_version(2:0)
dmd_type(3:0)
dmd_speed_sel(1:0)
dmd_irq
DLPU125 – JUNE 2023
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Table 3-2. Data Load Control Signals (continued)
Apps FPGA I/O
out

Table 3-3. Reset and Block Clear Signals

Apps FPGA I/O
out
out
out
out
in
Apps FPGA I/O
out
out
in
in
Table 3-5. The ddc_version, DMD_type, and DMD_irq signals are

Table 3-5. DLPC910 Status-Info Signals

Apps FPGA I/O
in
in
in
in
Copyright © 2023 Texas Instruments Incorporated
Function
Top/bottom image flip on DMD
Function
block address
block mode
dual and quad block control
DMD reset pulse watch dog timer enable
DMD mirror clocking pulse (MCP) in progress
Function
DLPC910 controller reset
DLPC910 PWR_FLOAT
DLPC910 configuration from SPI Flash status
DLPC910 initialization active status
Function
DLPC910 firmware version
DLPC910 DMD type
Apps/DLPC910 LVDS speed select jumpers
DMD irq status signal
®
DLP DLPC910 Apps FPGA Guide
Interfaces
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