Cmt-Ape Interchip Communication - Texas Instruments OMAP5912 Reference Manual

Multimedia processor device overview and architecture

Hide thumbs Also See for OMAP5912:

Table of Contents

OMAP5912 Description

Synchronous Serial Interconnect

CMT-APE Interchip Communication

Introduction

The synchronous serial interconnect (SSI) peripheral enables OMAP5912 to

exchange information with an external modem. It enables a full duplex

interface, using a synchronous serial interconnect protocol (SSI). This

protocol consists of a transmitter and a receiver.

On the modem side, there is also a receiver and a transmitter.

The SSI module includes:

One instance of each SST and SSR module

To enable a CMT-APE interface, an additional output generates a wake-up

signal to the CMT chip on the SSI interface. This output is driven by an OR

gate between 8-bit GPIO3 (GPIO51 to GPIO58) output lines. The CMT

chip can also wake up the APE chip with a dedicated GPIO (via its

asynchronous interrupt detection).

Table of Contents