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TMS320DM355
Texas Instruments TMS320DM355 Manuals
Manuals and User Guides for Texas Instruments TMS320DM355. We have
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Texas Instruments TMS320DM355 manuals available for free PDF download: User Manual, Instruction
Texas Instruments TMS320DM355 User Manual (175 pages)
Digital Media System-on-Chip (DMSoC) ARM Subsystem
Brand:
Texas Instruments
| Category:
I/O Systems
| Size: 1.13 MB
Table of Contents
Table of Contents
3
Preface
13
1 Introduction
16
Device Overview
16
Block Diagram
16
ARM Subsystem in DM355
17
DM355 Functional Block Diagram
17
2 ARM Subsystem Overview
18
Purpose of the ARM Subsystem
18
Components of the ARM Subsystem
18
References
19
DM355 ARM Subsystem Block Diagram
19
3 ARM Core
20
Introduction
20
Operating States/Modes
21
Processor Status Registers
21
Exceptions and Exception Vectors
22
The 16-BIS/32-BIS Concept
22
16-BIS/32-BIS Advantages
22
Exception Vector Table for ARM
22
Coprocessor 15 (CP15)
23
Addresses in an ARM926EJ-S System
23
Different Address Types in ARM System
23
Memory Management Unit
24
Caches and Write Buffer
25
Tightly Coupled Memory
26
ITCM/DTCM Memory Map
26
Embedded Trace Support
27
ITCM/DTCM Size Encoding
27
ETM Part Descriptions
27
4 Memory Mapping
29
Memory Map
29
DM355 Memory Map
29
ARM Internal Memories
30
External Memories
30
MPEG/JPEG Coprocessor (MJCP)
31
Peripherals
31
DM355 ARM Configuration Bus Access to Peripherals
31
Memory Interfaces Overview
33
Ddr2 Emif
33
External Memory Interface
33
5 Device Clocking
35
Overview
35
Peripheral Clocking Considerations
36
DM355 Clocking Architecture
36
Video Processing Back End Clocking
37
USB Clocking
37
6 PLL Controllers (Pllcs)
38
PLL Controller Module
38
Pllc1
39
PLLC1 Output Clocks
39
Pllc2
40
PLLC1 Configuration in DM355
40
PLLC2 Output Clocks
40
PLLC Functional Description
41
Multipliers and Dividers
41
Bypass Mode
41
PLL Mode
41
PLLC2 Configuration in DM355
41
PLL Configuration
42
PLL Mode and Bypass Mode
42
Changing Divider / Multiplier Ratios
42
Clock Ratio Change and Alignment with Go Operation
43
PLL Power down and Wakeup
44
PLL Controller Register Map
44
Introduction
44
PLL and Reset Controller Module Instance Table
44
PLLC Registers
44
Peripheral ID Register (PID)
46
Peripheral ID Register (PID) Field Descriptions
46
PLL Control (PLLCTL)
47
PLL Control Register (PLLCTL)
47
PLL Control Register (PLLCTL) Field Descriptions
47
PLL Multiplier Control Register (PLLM)
48
PLL Multiplier Control Register (PLLM) Field Descriptions
48
PLL Pre-Divider Control Register (PREDIV)
49
PLL Pre-Divider Control (PREDIV) Field Descriptions
49
PLL Controller Divider 1 Register (PLLDIV1)
50
PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions
50
PLL Controller Divider 2 Register (PLLDIV2)
51
PLL Controller Divider 2 Register (PLLDIV2) Field Descriptions
51
PLL Controller Divider 3 Register (PLLDIV3)
52
PLL Controller Divider 3 Register (PLLDIV3) Field Descriptions
52
PLL Post-Divider Control Register (POSTDIV)
53
PLL Post-Divider Control (POSTDIV) Field Descriptions
53
Bypass Divider Register (BPDIV)
54
Bypass Divider Register (BPDIV) Field Descriptions
54
PLL Controller Command Register (PLLCMD)
55
PLL Controller Command Register (PLLCMD) Field Descriptions
55
PLL Controller Status Register (PLLSTAT)
56
PLL Controller Status (PLLSTAT) Field Descriptions
56
PLL Controller Clock Align Control Register (ALNCTL)
57
PLL Controller Clock Align Control (ALNCTL) Field Descriptions
57
PLLDIV Ratio Change Status Register (DCHANGE)
58
PLLDIV Ratio Change Status (DCHANGE)
58
PLLDIV Ratio Change Status (DCHANGE) Field Descriptions
58
Clock Enable Control Register (CKEN)
59
Clock Enable Control Register (CKEN) Field Descriptions
59
Clock Status Register (CKSTAT)
60
Clock Status Register (CKSTAT) Field Descriptions
60
SYSCLK Status Register (SYSTAT)
61
SYSCLK Status Register (SYSTAT) Field Descriptions
61
PLL Controller Divider 4 Register (PLLDIV4)
62
PLL Controller Divider 4 Register (PLLDIV4) Field Descriptions
62
7 Power and Sleep Controller
63
Introduction
63
DM355 Power Domain and Module Topolgy
63
DM355 Power and Sleep Controller (PSC)
63
DM355 Power Domain and Module Topology
64
Module Configuration
65
Power Domain and Module States Defined
66
Power Domain States
66
Module States
66
Executing State Transitions
67
Power Domain State Transitions
67
Module State Transitions
67
Icepick Emulation Support in the PSC
67
Icepick Emulation Commands
67
PSC Interrupts
68
Interrupt Events
68
PSC Interrupt Events
68
Interrupt Registers
69
Interrupt Handling
69
PSC Registers
71
Peripheral Revision and Class Information (PID)
72
Peripheral Revision and Class Information Register (PID)
72
Peripheral Revision and Class Information Register (PID) Field Descriptions
72
Interrupt Evaluation Register (INTEVAL)
73
Interrupt Evaluation Register (INTEVAL) Field Descriptions
73
Module Error Pending Register 0 (Mod 0 - 31) (MERRPR0)
74
Module Error Pending Register 0 (Mod 0 - 31) (MERRPR0) Field Descriptions
74
Module Error Pending Register 1 (Mod 32 - 41) (MERRPR1)
75
Module Error Pending Register 1 (Mod 32 - 41) (MERRPR1) Field Descriptions
75
Module Error Clear Register 0 (Mod 0-31) (MERRCR0)
76
Module Error Clear Register 0 (Mod 0-31) (MERRCR0) Field Descriptions
76
Module Error Clear Register 1 (Mod 32-41) (MERRCR1)
77
Module Error Clear Register 1 (Mod 32-41) (MERRCR1) Field Descriptions
77
Power Error Pending Register (PERRPR)
78
Power Error Pending Register (PERRPR) Field Descriptions
78
Power Error Clear Register (PERRCR)
79
Power Error Clear Register (PERRCR) Field Descriptions
79
External Power Control Pending Register (EPCPR)
80
External Power Control Pending Register (EPCPR) Field Descriptions
80
External Power Control Clear Register (EPCCR)
81
External Power Control Clear Register (EPCCR) Field Descriptions
81
Power Domain Transition Command Register (PTCMD)
82
Power Domain Transition Command Register (PTCMD) Field Descriptions
82
Power Domain Transition Status Register (PTSTAT)
83
Power Domain Transition Status Register (PTSTAT) Field Descriptions
83
Power Domain Status Register 0 (Pdstatn)
84
Power Domain Status N Register (Pdstatn)
84
Power Domain Status N Register (Pdstatn) Field Descriptions
84
Power Domain Control N Register 0 (Pdctln)
85
Power Domain Control N Register (Pdctln)
85
Power Domain Control N Register (Pdctln) Field Descriptions
85
Module Status N Register 0-41 (Mdstatn)
86
Module Status N Register (Mdstatn)
86
Module Status N Register 0-41 (Mdstatn) Field Descriptions
86
Module Control N Register 0-41 (Mdctln)
87
Module Control N Register 0-41 (Mdctln) Field Descriptions
87
8 Interrupt Controller
88
Introduction
88
Interrupt Mapping
88
AINTC Interrupt Connections
88
INTC Methodology
89
Interrupt Mapping
90
Interrupt Prioritization
90
AINTC Functional Diagram
90
Vector Table Entry Address Generation
91
Clearing Interrupts
91
Interrupt Entry Table
91
Enabling and Disabling Interrupts
92
Immediate Interrupt Disable / Enable
92
Delayed Interrupt Disable
92
INTC Registers
93
Interrupt Controller (INTC) Registers
93
Fast Interrupt Request Status Register 0 (FIQ0)
94
Interrupt Status of INT[31:0] (if Mapped to FIQ)
94
Interrupt Status of INT[31:0] (if Mapped to FIQ) Field Descriptions
94
Fast Interrupt Request Status Register 1 (FIQ1)
95
Interrupt Status of INT[63:32] (if Mapped to FIQ)
95
Interrupt Status of INT[63:32] (if Mapped to FIQ) Field Descriptions
95
Interrupt Request Status Register 0 (IRQ0)
96
Interrupt Status of INT[31:0] (if Mapped to IRQ)
96
Interrupt Status of INT[31:0] (if Mapped to IRQ) Field Descriptions
96
Interrupt Request Status Register 1 (IRQ1)
97
Interrupt Status of INT[31:0] (if Mapped to IRQ)
97
Interrupt Status of INT[31:0] (if Mapped to IRQ) Field Descriptions
97
Fast Interrupt Request Entry Address Register (FIQENTRY)
98
Fast Interrupt Request Entry Address Register (FIQENTRY) Field Descriptions
98
Interrupt Request Entry Address Register (IRQENTRY)
99
Interrupt Request Entry Address Register (IRQENTRY) Field Descriptions
99
Interrupt Enable Register 0 (EINT0)
100
Interrupt Enable Register 0 (EINT0) Field Descriptions
100
Interrupt Enable Register 1 (EINT1)
101
Interrupt Enable Register 1 (EINT1) Field Descriptions
101
Interrupt Operation Control Register (INTCTL)
102
Interrupt Operation Control Register (INTCTL) Field Descriptions
102
Eabase
103
EABASE Field Descriptions
103
Interrupt Priority Register 0 (INTPRI0)
104
Interrupt Priority Register 0 (INTPRI0) Field Descriptions
104
Interrupt Priority Register 1 (INTPRI1)
105
Interrupt Priority Register 1 (INTPRI1) Field Descriptions
105
Interrupt Priority Register 2 (INTPRI2)
106
Interrupt Priority Register 2 (INTPRI2) Field Descriptions
106
Interrupt Priority Register 3 (INTPRI3)
107
Interrupt Priority Register 3 (INTPRI3) Field Descriptions
107
Interrupt Priority Register 4 (INTPRI4)
108
Interrupt Priority Register 4 (INTPRI4) Field Descriptions
108
Interrupt Priority Register 5 (INTPRI5)
109
Interrupt Priority Register 5 (INTPRI5) Field Descriptions
109
Interrupt Priority Register 6 (INTPRI6)
110
Interrupt Priority Register 6 (INTPRI6) Field Descriptions
110
Interrupt Priority Register 7 (INTPRI7)
111
Interrupt Priority Register 7 (INTPRI7) Field Descriptions
111
9 System Control Module
112
Overview of the System Control Module
112
Device Identification
112
Device Configuration
112
Pin Multiplexing Control
112
Device Boot Configuration Status
113
ARM Interrupt and EDMA Event Multiplexing Control
113
Special Peripheral Status and Control
113
Timer64+ Control
113
USB PHY Control
114
VPSS Clock and DAC Control and Status
114
DDR I/O Timing Control and Status
114
Clock out Configuration Status
114
GIO De-Bounce Control
114
Power Managment
114
Deep Sleep Control
114
Bandwidth Management
115
Bus Master DMA Priority Control
115
DM355 Master Ids
115
DM355 Default Master Priorities
116
System Control Register Descriptions
117
Introduction
117
System Module (SYS) Registers
117
PINMUX0 - Pin Mux 0 (Video In) Pin Mux Register
118
PINMUX0 - Pin Mux 0 (Video In) Pin Mux Register Field Descriptions
118
PINMUX1 - Pin Mux 1 (Video Out) Pin Mux Register
120
PINMUX1 - Pin Mux 1 (Video Out) Pin Mux Register Field Descriptions
120
PINMUX2 - Pin Mux 2 (AEMIF) Pin Mux Register
122
PINMUX2 - Pin Mux 2 (AEMIF) Pin Mux Register Field Descriptions
122
PINMUX3 - Pin Mux 3 (Gio/Misc) Pin Mux Register
124
PINMUX3 - Pin Mux 3 (Gio/Misc) Pin Mux Register Field Descriptions
124
PINMUX3 - Pin Mux 3 (Gio/Misc) Pin Mux Register
126
PINMUX4 - Pin Mux 4 (Misc) Pin Mux Register
127
PINMUX4 - Pin Mux 4 (Misc) Pin Mux Register Field Descriptions
127
BOOTCFG - Boot Configuration
128
BOOTCFG - Boot Configuration Field Descriptions
128
ARM_INTMUX - ARM Interrupt Mux Control Register
129
ARM_INTMUX - ARM Interrupt Mux Control Register Field Descriptions
129
EDMA_EVTMUX - EDMA Event Mux Control Register
130
EDMA_EVTMUX - EDMA Event Mux Control Register Field Descriptions
130
DDR_SLEW - DDR Slew
131
DDR_SLEW - DDR Slew Field Descriptions
131
CLKOUT - CLKOUT Divisor / Output Control
132
CLKOUT - CLKOUT DIV/Out Control
132
CLKOUT - CLKOUT DIV/Out Control Field Descriptions
132
DEVICE_ID - Device ID
133
DEVICE_ID - Device ID Field Descriptions
133
VDAC_CONFIG - Video Dac Configuration
134
VDAC_CONFIG - Video Dac Configuration Field Descriptions
134
TIMER64_CTL - Timer64+ Input Control
135
TIMER64_CTL - Timer64+ Input Control Field Descriptions
135
USB_PHY_CTRL - USB PHY Control
136
USB_PHY_CTRL - USB PHY Control Field Descriptions
136
MISC - Miscellaneous Control
138
MISC - Miscellaneous Control Field Descriptions
138
MSTPRI0 - Master Priorities 0
139
MSTPRI0 - Master Priorities
139
MSTPRI0 - Master Priorities 0 Field Descriptions
139
MSTPRI1 - Master Priorities 1
140
VPSS_CLK_CTRL - VPSS Clock Mux Control
141
VPSS_CLK_CTRL - VPSS Clock Mux Control Field Descriptions
141
DEEPSLEEP - Deep Sleep Mode Configuration
142
DEEPSLEEP - Deep Sleep Mode Configuration Field Descriptions
142
DEBOUNCE[8] - De-Bounce for Gio[N] Input
143
DEBOUNCE[8] - De-Bounce for Gio[N] Input Field Descriptions
143
VTPIOCR - VTP IO Control Register
144
VTP IO Control Register (VTPIOCR)
144
VTPIOCR - VTP IO Control Field Descriptions
144
10 Reset
145
Reset Overview
145
Reset Pins
145
Reset Types
145
Types of Reset
146
Power-On Reset (POR)
146
Warm Reset
146
Max Reset
147
System Reset
147
Module Reset
147
Default Device Configurations
147
Device Configuration Pins
147
PLL Configuration
148
Module Configuration
148
ARM Boot Mode Configuration
148
AEMIF Configuration
149
11 Boot Modes
150
Boot Modes Overview
150
Features
150
Boot Modes Overview
151
Functional Block Diagram
152
ARM ROM Boot Modes
152
NAND Boot Mode
152
Boot Mode Functional Block Diagram
152
NAND Boot Flow
153
NAND UBL Descriptor
154
UBL Signatures and Special Modes
154
Bit ECC Format and Bit 10 to 8-Bit Compression Algorithm
155
Bit ECC Format for 2048+64 Byte Page Size
156
NAND Boot Mode Flow Chart
158
ARM NAND ROM Boot Loader Example
159
Descriptor Search for ARM NAND Boot Mode
160
NAND Ids Supported
160
MMC/SD Boot Mode
162
MMC/SD Boot Mode Overview
163
MMC/SD UBL Descriptor
164
MMC/SD UBL Signatures and Special Modes
164
MMC/SD Boot Mode Flow Chart
165
ARM MMC/SD ROM Boot Loader Example
166
UART Boot Mode
167
Descriptor Search for ARM MMC/SD Boot Mode
167
UART Boot Mode Handshake
168
UART Data Sequences
169
Host Utility Timing
170
Host Utility Data Format
170
CRC32 Table Transfer
170
12 Power Management
171
Overview
171
PSC and PLLC Overview
171
Power Management Features
171
Clock Management
172
Module Clock Disable
172
Module Clock Frequency Scaling
172
PLL Bypass and Power down
172
ARM Sleep Mode Management
172
ARM Wait-For-Interrupt Sleep Mode
172
System Sleep Modes
173
Deep Sleep Mode
173
Fast NAND Boot Mode
173
I/O Management
174
USB Phy Power down
174
Video DAC Power down
174
DDR Selft-Refresh and Power down
174
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Texas Instruments TMS320DM355 Instruction (155 pages)
Texas Instruments Digital Media System-on-Chip (DMSoC) Product Preview
Brand:
Texas Instruments
| Category:
Computer Hardware
| Size: 1.66 MB
Table of Contents
Features
1
Description
3
1 TMS320DM355 Digital Media System-On-Chip (Dmsoc)
4
Functional Block Diagram
4
Table of Contents
5
2 Device Overview
6
Device Characteristics
6
Memory Map Summary
7
Pin Assignments
9
Pin Functions
13
Serial Interface
31
Pin List
36
Device Support
55
3 Detailed Device Description
59
ARM Subsystem Overview
59
Arm926Ej-S Risc Cpu
60
ARM Interrupt Controller (AINTC)
63
Device Clocking
65
PLL Controller (PLLC)
73
Power and Sleep Controller (PSC)
77
System Control Module
77
Pin Multiplexing
78
Device Reset
79
Default Device Configurations
80
Device Boot Modes
83
Power Management
85
64-Bit Crossbar Architecture
87
MPEG/JPEG Overview
90
4 Device Operating Conditions
91
Absolute Maximum Ratings over Operating Case Temperature Range (Unless Otherwise Noted)
91
Sprs463A – September 2007 – Revised September
91
Submit Documentation Feedback
91
Recommended Operating Conditions
92
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92
Electrical Characteristics over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
93
Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
93
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93
5 Peripheral Information and Electrical Specifications
94
Parameter Information Device-Specific Information
94
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94
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95
Recommended Clock and Control Signal Transition Behavior
96
Power Supplies
96
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96
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97
Reset
98
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98
Oscillators and Clocks
99
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99
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100
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101
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102
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103
General-Purpose Input/Output (GPIO)
104
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104
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105
External Memory Interface (EMIF)
106
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106
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107
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108
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109
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110
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111
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112
MMC/Sd
113
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113
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114
Video Processing Sub-System (VPSS) Overview
115
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115
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116
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117
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118
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119
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120
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121
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122
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123
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125
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126
Usb 2.0
127
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127
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128
Universal Asynchronous Receiver/Transmitter (UART)
129
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129
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130
Serial Port Interface (SPI)
131
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131
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132
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133
Inter-Integrated Circuit (I2C)
134
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134
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135
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136
Audio Serial Port (ASP)
137
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137
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138
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139
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140
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141
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142
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143
Timer
144
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144
Pulse Width Modulator (PWM)
145
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145
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146
Real Time out (RTO)
147
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147
Ieee 1149.1 Jtag
148
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148
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149
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150
Revision History
151
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151
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152
Mechanical Data
153
Thermal Data for ZCE
153
Packaging Information
153
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153
Important Notice
155
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