ST STM32WL55JC Reference Manual page 1135

RM0453
RX line
Sample
clock (x8)
Framing error
A framing error is detected when the stop bit is not recognized on reception at the expected
time, following either a de-synchronization or excessive noise.
When the framing error is detected:
•
the FE bit is set by hardware;
•
the invalid data is transferred from the Shift register to the USART_RDR register
(RXFIFO in case FIFO mode is enabled).
•
no interrupt is generated in case of single byte communication. However this bit rises at
the same time as the RXNE bit (RXFNE in case FIFO mode is enabled) which itself
generates an interrupt. In case of multibuffer communication an interrupt is issued if the
EIE bit is set in the USART_CR3 register.
The FE bit is reset by writing '1' to the FECF in the USART_ICR register.
Note: Framing error is not supported in SPI mode.
Universal synchronous/asynchronous receiver transmitter (USART/UART)
Figure 312. Data sampling when oversampling by 8
1 2
Table 240. Noise detection from sampled data
Sampled value
000
001
010
011
100
101
110
111
sampled values
3 4
3/8
One bit time
NE status
0
1
1
1
1
1
1
0
RM0453 Rev 2
5 6 7
2/8
3/8
Received bit value
8
MSv31153V1
0
0
0
1
0
1
1
1
1135/1454
1257