Figure 316. Break Detection In Lin Mode (11-Bit Break Length - Lbdl Bit Is Set) - ST STM32WL55JC Reference Manual

RM0453
Figure 319. USART data clock timing diagram in synchronous master mode
Idle or
preceding
transmission
Clock (CPOL=0,
CPHA=0)
Clock (CPOL=0,
CPHA=1)
Clock (CPOL=1,
CPHA=0)
Clock (CPOL=1,
CPHA=1)
Data on TX
(from master)
Data on RX
(from slave)
Capture
strobe
Slave mode
The synchronous slave mode is selected by programming the SLVEN bit in the
USART_CR2 register to '1'. In synchronous slave mode, the following bits must be kept
cleared:
•
LINEN and CLKEN bits in the USART_CR2 register,
•
SCEN, HDSEL and IREN bits in the USART_CR3 register.
In this mode, the USART can be used to control bidirectional synchronous serial
communications in slave mode. The CK pin is the input of the USART in slave mode.
Note: When the peripheral is used in SPI slave mode, the frequency of peripheral clock source
(usart_ker_ck_pres) must be greater than 3 times the CK input frequency.
The CPOL bit and the CPHA bit in the USART_CR2 register are used to select the clock
polarity and the phase of the external clock, respectively (see
An underrun error flag is available in slave transmission mode. This flag is set when the first
clock pulse for data transmission appears while the software has not yet loaded any value to
USART_TDR.
The slave supports the hardware and software NSS management.
Universal synchronous/asynchronous receiver transmitter (USART/UART)
Start
0 1
Start LSB
0 1
LSB
RM0453 Rev 2
(M bits = 01)
M bits =01 (9 data bits)
2 3 4 5
2 3 4 5
*LBCL bit controls last data pulse
Idle or next
Stop
transmission
*
*
*
*
6 7 8
MSB Stop
6 8
7
MSB
*
Figure 320).
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