ST STM32WL55JC Reference Manual page 1189

RM0453
Bits 31:28 Reserved, must be kept at reset value.
Bit 27 TXFT: TXFIFO threshold flag
Bit 26 RXFT: RXFIFO threshold flag
Note: When the RXFTCFG threshold is configured to '101', RXFT flag is set if 16 data are
Bit 25 TCBGT: Transmission complete before guard time flag
Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at
Bit 24 RXFF: RXFIFO full
Bit 23 TXFE: TXFIFO empty
Universal synchronous/asynchronous receiver transmitter (USART/UART)
This bit is set by hardware when the TXFIFO reaches the threshold programmed in
TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An
interrupt is generated if the TXFTIE bit = 1 (bit 31) in the USART_CR3 register.
0: TXFIFO does not reach the programmed threshold.
1: TXFIFO reached the programmed threshold.
This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3
register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and
one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit = 1 (bit
27) in the USART_CR3 register.
0: Receive FIFO does not reach the programmed threshold.
1: Receive FIFO reached the programmed threshold.
available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the
17th received data does not cause an overrun error. The overrun error occurs after
receiving the 18th data.
This bit is set when the last data written in the USART_TDR has been transmitted correctly
out of the shift register.
It is set by hardware in Smartcard mode, if the transmission of a frame containing data is
complete and if the smartcard did not send back any NACK. An interrupt is generated if
TCBGTIE = 1 in the USART_CR3 register.
This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or
by a write to the USART_TDR register.
0: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is
received from the card)
1: Transmission is complete successfully (before Guard time completion and there is no
NACK from the smart card).
reset value. If the USART supports the Smartcard mode and the Smartcard mode is
enabled, the TCBGT reset value is '1'. Refer to
on page 1120.
This bit is set by hardware when the number of received data corresponds to
RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register.
An interrupt is generated if the RXFFIE bit = 1 in the USART_CR1 register.
0: RXFIFO not full.
1: RXFIFO Full.
This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one
data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4)
in the USART_RQR register.
An interrupt is generated if the TXFEIE bit = 1 (bit 30) in the USART_CR1 register.
0: TXFIFO not empty.
1: TXFIFO empty.
RM0453 Rev 2
Section 35.4: USART implementation
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