ST STM32WL55JC Reference Manual page 1181

RM0453
Bits 31:29 TXFTCFG[2:0]: TXFIFO threshold configuration
Bit 28 RXFTIE: RXFIFO threshold interrupt enable
Bits 27:25 RXFTCFG[2:0]: Receive FIFO threshold configuration
Bit 24 TCBGTIE: Transmission Complete before guard time, interrupt enable
Note: If the USART does not support the Smartcard mode, this bit is reserved and must be
Bit 23 TXFTIE: TXFIFO threshold interrupt enable
Bit 22 WUFIE: Wakeup from low-power mode interrupt enable
Note: WUFIE must be set before entering in low-power mode.
Universal synchronous/asynchronous receiver transmitter (USART/UART)
000:TXFIFO reaches 1/8 of its depth
001:TXFIFO reaches 1/4 of its depth
010:TXFIFO reaches 1/2 of its depth
011:TXFIFO reaches 3/4 of its depth
100:TXFIFO reaches 7/8 of its depth
101:TXFIFO becomes empty
Remaining combinations: Reserved
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated when Receive FIFO reaches the threshold programmed in
RXFTCFG.
000:Receive FIFO reaches 1/8 of its depth
001:Receive FIFO reaches 1/4 of its depth
010:Receive FIFO reaches 1/2 of its depth
011:Receive FIFO reaches 3/4 of its depth
100:Receive FIFO reaches 7/8 of its depth
101:Receive FIFO becomes full
Remaining combinations: Reserved
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated whenever TCBGT=1 in the USART_ISR register
kept at reset value. Refer to
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated when TXFIFO reaches the threshold programmed in
TXFTCFG.
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated whenever WUF = 1 in the USART_ISR register
If the USART does not support the wakeup from Stop feature, this bit is reserved and
must be kept at reset value. Refer to
page 1120.
Section 35.4: USART implementation on page
Section 35.4: USART implementation on
RM0453 Rev 2
1120.
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