Adc Sample Time Register 1 (Adc_Smpr1); Adc Sample Time Register 2 (Adc_Smpr2) - ST STM32F410 Reference Manual

Analog-to-digital converter (ADC)
11.12.4

ADC sample time register 1 (ADC_SMPR1)

Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
15 14 13
SMP15_0 SMP14[2:0]
rw rw rw
Bits 31: 27 Reserved, must be kept at reset value.
Bits 26:0 SMPx[2:0]: Channel x sampling time selection
These bits are written by software to select the sampling time individually for each channel.
During sampling cycles, the channel selection bits must remain unchanged.
Note: 000: 3 cycles
11.12.5

ADC sample time register 2 (ADC_SMPR2)

Address offset: 0x10
Reset value: 0x0000 0000
31 30 29
Res. Res. SMP9[2:0]
rw
15 14 13
SMP5_0 SMP4[2:0]
rw rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:0 SMPx[2:0]: Channel x sampling time selection
Note: 000: 3 cycles
234/771
28 27 26 25
Res. Res. SMP18[2:0]
rw rw
12 11 10 9
SMP13[2:0]
rw rw rw rw
001: 15 cycles
010: 28 cycles
011: 56 cycles
100: 84 cycles
101: 112 cycles
110: 144 cycles
111: 480 cycles
28 27 26 25
SMP8[2:0]
rw rw rw rw
12 11 10
SMP3[2:0]
rw rw rw rw
These bits are written by software to select the sampling time individually for each channel.
During sample cycles, the channel selection bits must remain unchanged.
001: 15 cycles
010: 28 cycles
011: 56 cycles
100: 84 cycles
101: 112 cycles
110: 144 cycles
111: 480 cycles
24 23 22
SMP17[2:0]
rw rw rw
8 7 6
SMP12[2:0]
rw rw rw
24 23 22
SMP7[2:0]
rw rw rw
9 8 7 6
SMP2[2:0]
rw rw rw
RM0401 Rev 3
21 20 19 18
SMP16[2:0]
rw rw rw rw
5 4 3 2
SMP11[2:0]
rw rw rw rw
21 20 19 18
SMP6[2:0]
rw rw rw rw
5 4 3 2
SMP1[2:0]
rw rw rw rw
RM0401
17 16
SMP15[2:1]
rw rw
1 0
SMP10[2:0]
rw rw
17 16
SMP5[2:1]
rw rw
1 0
SMP0[2:0]
rw rw