Register Of Dtp/External Interrupt - Fujitsu F2MC-16LX Hardware Manual

18.2

Register of DTP/External Interrupt

This section describes the configuration and functions of registers used for the DTP
and external interrupts.
Register List of DTP/external Interrupt
Figure 18.2-1 shows the register list of the DTP/external interrupts.
Address : 00003C
Address : 00003D
Address : 00003E
Address : 00003F
DTP/interruption Permission Register (ENIR: Enable Interrupt Request Register)
Figure 18.2-2 shows the bit configuration of the DTP and enable interrupt register (ENIR).
Figure 18.2-2 Bit Configuration of the DTP and the Enable Interrupt Request Register (ENIR)
ENIR
Address : 00003C
The DTP and the enable interrupt register (ENIR) determine to issue the request to the interrupt controller
by using the device terminal as the external interrupt and the DTP request input. The terminal
corresponding to the bits set to "1" in the ENIR register is used to input an external interrupt or DTP
request to issue the requests to the interrupt controller. The terminal corresponding to the bits set to "0"
holds the external interrupt or DTP request input factor but issues no request to the interrupt controller.
Figure 18.2-1 Register List of DTP/external Interrupt
7 6 5
bit
EN7 EN6 EN5 EN4
H
15 14 13
bit
ER7 ER6 ER5 ER4
H
7 6 5
bit
LB3 LA3 LB2 LA2
H
15 14 13
bit
LB7 LA7 LB6 LA6
H
7 6
EN7 EN6
H
R/W R/W
CHAPTER 18 DTP/EXTERNAL INTERRUPT
4 3 2 1
EN3 EN2 EN1
12 11 10 9
ER3 ER2 ER1
4 3 2 1
LB1 LA1 LB0
12 11 10 9
LB5 LA5 LB4
5 4 3 2
EN5 EN4 EN3 EN2
R/W R/W R/W R/W
0
DTP/Interrupt register
EN0
(ENIR)
8
DTP/Interrupt register
ER0
(EIRR)
0
Request level setting register
LA0
(ELVR)
8
Request level setting register
LA4
(ELVR)
1 0
Initial value
EN1 EN0
00000000
B
R/W R/W
423