External Interrupt Request Register (Eirrn) - Fujitsu FR60 Hardware Manual

CHAPTER 10 EXTERNAL INTERRUPT AND NMI CONTROLLER
10.2.2

External Interrupt Request Register (EIRRn)

The external interrupt request register (EIRRn) indicates the presence or absence of a
corresponding external interrupt request when reading from this register and the
contents of the flip-flop (NMI flag) that indicates this interrupt request are cleared when
writing to this register.
■ Bit Configuration of External Interrupt Request Register (EIRRn)
The bit configuration of the external interrupt request register is shown below.
EIRR0 address :000040
EIRR1 address :0000D0
When the EIRR register is read, operation depends on the value that is read.
If the value read from a bit is "1", there is an external interrupt request at the pin corresponding to the bit.
Write "0" to this register to clear the request flip-flop of the corresponding bit.
Writing "1" to this has no effect.
For a read by a read modify write instruction, "1" is read.
The NMI flag cannot be read or written to by a user.
Note:
For details on the NMI flag, see Figure 10.3-4 in Section "10.3 Operation of the External Interrupt
and NMI Controller".
346
15 14 13
bit
ER7 ER6 ER5
H
15 14 13
bit
ER15 ER14 ER13
H
12 11 10
ER4 ER3 ER2 ER1
12 11 10
ER12 ER11 ER10 ER9
9 8 Initial value
00000000
ER0
B
[R/W]
9 8 Initial value
00000000
ER8
B
[R/W]