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3.8.2
ICR (Interrupt Control Register)
The interrupt control register (ICR) is provided in the interrupt controller to set a level
for each interrupt request. This register is prepared for each interrupt request input.
The register is mapped in the I/O space and accessed from the CPU through a bus.
■ ICR Bit Configuration
ICR00 to ICR47
Address
000440
to 00046F
H
[bit4] ICR4
ICR4 always contains "1".
[bit3 to bit0] ICR3 to ICR0
These are the lower four bits indicating the interrupt level of the corresponding interrupt source.
The ICR, consisting of these bits and bit4, can set a value between 16 and 31.
These bits can be read and written.
■ ICR Mapping
Table 3.8-2 shows the relationship between the interrupt source, interrupt control register, and interrupt
vector.
See CHAPTER 5 "INTERRUPT CONTROLLER" for detail of the interrupt.
Table 3.8-2 Interrupt Sources, Interrupt Control Registers, and Interrupt Vectors
Interrupt
source
IRQ00
IRQ01
IRQ02
...
...
IRQ45
IRQ46
IRQ47
TBR initial value: "000FFC00
7
6
5
–
–
–
–
–
–
H
Interrupt control register
ICR00
00000440
ICR01
00000441
ICR02
00000442
...
...
ICR45
0000046D
ICR46
0000046E
ICR47
0000046F
"
H
CHAPTER 3 CPU AND CONTROL UNITS
4
3
2
ICR4
ICR3
ICR2
R
R/W
R/W
Corresponding interrupt vector
Number
Hex
Dec
10
16
H
H
11
17
H
H
12
18
H
H
...
...
...
...
...
...
3D
61
H
H
3E
62
H
H
3F
63
H
H
1
0
Initial value
ICR1
ICR0
---11111
R/W
R/W
[R/W, R]
Address
TBR + 3BC
H
TBR + 3B8
H
TBR + 3B4
H
...
...
TBR + 308
H
TBR + 304
H
TBR + 300
H
B
51
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