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CHAPTER 12 DTP/external interrupt
12.3.1
DTP/external interrupt factor register (EIRR)
This register holds DTP/external interrupt factors.
When a valid signal is input to the DTP/external interrupt pin or RX pin, the
corresponding interrupt request flag bit is set to "1".
I DTP/external interrupt factor register (EIRR)
15
13
14
R/W
R/W
R/W
R/W : Read/Write
X : Undefined
- : Unused
Table 12.3-2 Function of DTP/External Interrupt Factor Register (EIRR)
bit name
bit8,
ER7 to ER4, ER0:
bit12
DTP/External interrupt
to
request flag bits
bit15
bit9 to
Unused bits
bit11
334
Figure 12.3-2 DTP/external interrupt factor register (EIRR)
12
11
10
9
8
R/W
-
-
-
R/W
bit15 to bit12,bit8
These bits are set to "1" when the edges or level signals set by the detection
condition select bits (ELVR: LB, LA) in the detection level setting register are input
to the DTP/external interrupt pin or RX pin.
When set to "1": When the DTP/external interrupt request enable bit (ENIR:
EN) is set to "1", an interrupt request is generated to the corresponding DTP/
external interrupt channel.
When set to "0": The bit is cleared.
When the bit is set to "1": No effect.
Note:
The bit returns "1" when read by a read modify write instruction.
If more than one DTP/external interrupt request is enabled (ENIR: EN = 1),
clear only the bit in the channel that accepts an interrupt (EIRR: ER = 0).No
other bits must be cleared unconditionally.
Reference:
2
When the (EI
OS) is started, the interrupt request flag bit is automatically
cleared after the completion of data transfer (EIRR: ER = 0)
Read: The value is undefined.
Write: No effect
Reset value
XXXXXXXX
B
DTP/external interrupt request flag bit
ER7 to ER4,ER0
Read
0
Without DTP/external interrupt
1
With DTP/external interrupt
Function
Write
Clear ER bit
No effection
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