Interrupt/Dtp Cause Register (Eirr: External Interrupt Request Register); Request Level Setting Register (Elvr: External Level Register) - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

9.3.2 Interrupt/DTP cause register (EIRR: External interrupt request register)

Interrupt/DTP cause register
Address : 000031
Read/write
Initial value
When read, EIRR indicates the current external interrupt/DTP requests. When written, EIRR clears the
flip-flop values indicating those requests. External interrupt/DTP requests exist at the pins corresponding
to the '1' bits of this register. Writing '0' to a bit of this register clears the corresponding request flip-flop
value. Writing '1' performs no operation. '1' is always read from this register by a read-modify-write
instruction.

9.3.3 Request level setting register (ELVR: External level register)

Request level setting register (Lower Byte)
Address : 000032
Read/write
Initial value
Request level setting register (Higher Byte)
Address : 000033
Read/write
Initial value
ELVR is used to select a request detection factor. Each pin is assigned two bits as described in the table
below. If a request is to be detected based on a level, the register value is maintained while the input is
active even when it is cleared.
MB90580 Series
15 14
ER7 ER6 ER5
H
(R/W) (R/W) (R/W)
(X) (X)
7 6
LB3 LA3 LB2
H
(R/W) (R/W) (R/W)
(0) (0)
15 14
LB7 LA7 LB6
H
(R/W) (R/W) (R/W)
(0) (0)
LBx LAx
0 0
0 1
1 0
1 1
13 12 11
ER4 ER3 ER2
(R/W) (R/W) (R/W)
(X) (X) (X) (X)
5 4 3
LA2 LB1
(R/W) (R/W) (R/W)
(0) (0) (0)
13 12 11
LA6 LB5 LA5
(R/W) (R/W) (R/W)
(0) (0) (0)
Interrupt request detection factor
L level pin input
H level pin input
Rising edge pin input
Falling edge pin input
9.3 Registers and Register Details
10 9 8
ER1 ER0
EIRR
(R/W) (R/W)
(X) (X)
2 1 0
LA1 LB0 LA0
(R/W) (R/W)
(0) (0) (0)
10 9 8
LB4 LA4
ELVR (HIGH)
(R/W) (R/W)
(0) (0) (0)
Chapter 9: DTP/External Interrupt
Bit number
Bit number
ELVR (LOW)
Bit number
111