Mb89120/120A Series Block Diagram; Figure 1.4-1 Mb89120/120A Series Block Diagram - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 1 OVERVIEW
1.4

MB89120/120A Series Block Diagram

Figure 1.4-1 shows the block diagram of the MB89120/120A series.
MB89120/120A Series Block Diagram
X0
X1
X0A
X1A
P00/(INT20) to
8
P07/(INT27)
8
P10 to P17
8
P20 to P27
MOD0, MOD1, V
8

Figure 1.4-1 MB89120/120A Series Block Diagram

Main clock
Oscillator
(at 4.2 MHz max.)
Clock controller
Sub clock
Low-power
oscillator
(32.768 kHz)
Watch prescaler
CMOS I/O port
External interrupt 2
(wake-up)
8
Only in MB89120A
series
CMOS output port
RAM
F 2 MC-8L
CPU
ROM
Other pins
, V
CC SS
Timebase
timer
Reset circuit
(Watchdog timer)
16-bit timer/counter
8-bit
timer/counter 2
8-bit
timer/counter 1
8-bit serial I/O
External interrupt 1
Remote-control
transmission
frequency generator
Only in MB89120A
series
Buzzer output
CMOS I/O port
N-ch open-drain output port
RST
P34/TO/INT0
P33/EC/SCO
P30/SCK
P32/SI
P31/SO
P35/INT1
P36/INT2
P37/BZ/(RCO)
4
P40 to P43