Block Diagram - Fujitsu MB90335 Series Hardware Manual

MB90335 Series
1.2

Block Diagram

Figure 1.2-1 shows the block diagram of a MB90335 series.
■ Block Diagram of the MB90335 Series
X0,X1
RST
DVP
DVM
HVP
HVM
HCON
UTEST
P27/PPG3
P26/PPG2
P25/PPG1
P24/PPG0
P23
P22
P21
P20
P17 to P10
P07 to P00
Note:
In Figure 1.2-1, I/O ports share pins with each of built-in functional blocks. Any port used for built-in
module pin cannot be used as an I/O port.
CM44-10137-6E
Figure 1.2-1 Block Diagram of the MB90335 Series
Clock
control circuit 2
F MC-16LX core
RAM(4Kbyte)*
ROM(64Kbyte)*
Interrupt controller
USB HOST
USB function
Port 2
8/16-bit PPG
8/16bit PPG
(ch.0,ch.1)
(ch0,ch1)
Port 1
Port 0
FUJITSU MICROELECTRONICS LIMITED
CPU
Port 6
External interrupt
(ch.0 to ch.7)
16-bit PWC
Extended I/O serial
interface
2
I C interface
(ch.0)
Port 5
Port 4
UART(ch.0,ch.1)
16-bit reload
timer (ch.0)
Vss Vcc
CHAPTER 1 OVERVIEW
1.2 Block Diagram
P67/INT7/SDA0
P66/INT6/SCL0
P65/INT5/PWC
P64/INT4/SCK
P63/INT3/SOT
P62/INT2/SIN
P61/INT1
P60/INT0
P55 to P50
P47/SCK1
P46/SOT1
P45/SIN1
P44/SCK0
P43/SOT0
P42/SIN0
P41/TOT0
P40/TIN0
Other pins
MD0 MD1 MD2
*: Maximum value
7