Block Diagram; Figure 1.3A Block Diagram Of Mb90580 Series; Chapter 1 Overview - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

1.3 Block Diagram

1.3 Block Diagram
X0,X1
4
Clock control
X0A,X1A
TX
RX
8
P00-07/AD00-07
8
P10-17/AD08-15
8
P20-27/A16-23
P30/ALE
P31/RDX
P32/WRLX
P33/WRHX
P34/HRQ
P35/HAKX
P36/RDY
P37/CLK
P40/SIN0
P41/SOT0
P42/SCK0
P43/SIN1
P44/SOT1
P45/SCK1
P46/ADTG6
P47
P50/AN0/SIN3
P51/AN1/SOT3
P52/AN2/SCK3
P53/AN3
P54/AN4/SIN4
P55/AN5/SOT4
P56/AN6/SCK4
P57/AN7
AVCC
2
AVRH,AVRL
AVSS
Vss x 3, Vcc x 2, MD0-2 and C
Note: P00 to P07 (8 channels): With registers that can be used as input pull-up resistors
P10 to P17 (8 channels): With registers that can be used as input pull-up resistors
P60 to P65 (6 channels): With registers that can be used as input pull-up resistors
P40 to P47 (8 channels): With registers that can be used as open drains
4 Chapter 1: Overview
2
F MC-16LX series core
circuit
IEBUS™
Controller
External
Bus
Interface
Communication
prescaler x 5
UART
x 5 channels
A/D converter
8 (10 bits)
RAM
ROM
ROM Correction
ROM Mirroring
Other pins

Figure 1.3a Block Diagram of MB90580 Series

CPU
(Watch-dog timer)
Hardware Standby circuit
Timebase timer
Delayed Interrupt generator
Interrupt controller
CMOS I/O PORT A
I/O timer
16-bit OCU x 2 channels
16-bit ICU x 4 channels
16-bit free-run timer
16-bit reload timer
x 3 channels
Noise Filter
16-bit PWC Timer
CMOS I/O PORT 9
8+8 PPG
x 1 channel
Clock Monitor
CMOS I/O PORT 6
DTP/External interrupt
CMOS I/O PORT 8
CMOS I/O PORT 7
D/A converter (8 bits)
x 2 channels
Reset Circuit
RSTX
HSTX
3
PA0-2
P90/TIN0/IN0
P91/TIN1/IN1
P92/TIN2/IN2
P93/TOT0/IN3
P94/TOT1/OUT0
P95/TOT2/OUT1
P96/PWC
P97/POT
P63/PPG0
2
P64/PPG1
P65/CKOT
P60/SIN2
P61/SOT2
P62/SCK2
8
P80/IRQ0 -
P87/IRQ7
P71
P72
P73/DA00
P74/DA01
DVRH
DVSS
MB90580 series