Interface Trap Density - Keithley 4200A-SCS Reference Manual

Model 4200A-SCS Parameter Analyzer Reference Manual

Interface trap density

Interface trapped charges (Q
Si-SiO interface. These charges are one of four general types associated with the Si-SiO
2
Interface charges interact electrically with the silicon substrate, which affects MOSFET channel
carrier mobility.
Band bending versus gate voltage
As a preliminary step, surface potential (ψ
column of the array. Surface potential is calculated as follows:
Where:
•
(ψ -ψ
S
•
C = quasistatic capacitance (pF)
Q
•
C
OX
•
V
STEP
•
V = gate-substrate voltage (V)
GS
Note that the (ψ
#1) to the last array row (V
readings in the sweep, which is determined by the Start, Stop, and Step voltages.
Once (ψ
reference point and is set to 0 by subtracting that value from each entry in the (ψ
changing each element in the column to ψ
4200A-901-01 Rev. C / February 2017
) are electrons or holes trapped in localized surface states near the
it
) = surface potential (V)
0
= oxide capacitance (pF)
= step voltage (V)
-ψ ) value is accumulated as the column is built, from the first row of the array (V
S 0
last). The number of rows will, of course, depend on the number of
GS
-ψ ) values are stored in the array, the value of (ψ
S 0
Appendix D: Using a Model 82 C-V System
is calculated with the results placed in the ψ
-ψ ) vs. V
S 0 GS
-ψ ) at the flatband voltage is used as a
S 0
.
S
iterface.
2
S
GS
-ψ ) column,
S 0
D-55