Hci Degradation: Background Information; Configuration Sequence For Subsite Cycling - Keithley 4200A-SCS Reference Manual

Model 4200A-SCS Parameter Analyzer Reference Manual

HCI degradation: Background information

HCI degradation is one of the most important device issues facing the semiconductor industry. Small
gate length and process variations in the semiconductor process can result in dramatic degradation in
HCI device performance. In the last few years, HCI lifetimes have reduced dramatically. In some
cases, drive current lifetimes have dropped from years to weeks. HCI effects are enhanced with
device scaling (this includes a reduction in device gate length). This means that HCI effects will be an
even greater concern in the future. HCI is clearly an important semiconductor issue and the need to
monitor HCI on a regular basis is a critical test requirement.
Hot carrier damage occurs in MOS devices when carriers (electrons or holes) are accelerated in the
channel. In short channel devices, these electrons/holes attain velocities high enough to cause
impact ionization. Impact ionization, in turn, creates extra carriers in the MOS channel. These extra
carriers result in significant substrate currents and in some cases attain high enough energy to
overcome the semiconductor-oxide barrier and are trapped in the oxide. Most of the oxide carrier
trapping occurs at the drain edge where carrier velocity is maximized. These trapped channel
electrons can cause significant device performance asymmetry and shifts in critical device
parameters such as threshold voltage and device drive current. In some cases, as much as 10%
change in measured device parameters can occur within a few days.
The devices of today are becoming increasingly susceptible to hot carrier effects. In the past, the
linear drain current target value for successful hot carrier device performance was a 10% change in
10 years. Typically, manufactured devices can no longer meet this specification and as much as 10%
degradation in linear drain current can occur in a few days. Because of this fact, the semiconductor
manufacturer has even a greater need to monitor HCI effects.

Configuration sequence for subsite cycling

The following projects use subsite cycling:
•
hci-1-dut
•
hci-4-dut
•
nbti-1-dut
•
em-const-i
The process flow for these projects is shown in the figure below.
You can create a new project for subsite cycling or you can use one of the existing projects as a
starting point and change it as needed. For details, see
To configure the subsite for subsite cycling, refer to
4200A-901-01 Rev. C / February 2017
Appendix L: Wafer-level reliability testing
Set up a basic project
Configure Subsite Cycling
(on page 6-9).
(on page 6-148).
L-9