Keithley 4200A-SCS Reference Manual page 1366

Model 4200A-SCS Parameter Analyzer Reference Manual
Output variables
V_stress
I_stress
T_stress
q_stress
Q_bd
q_bd
v_bd
I_bd
t_bd
failure_mode
test_status
Details
Performs a Charge-to-Breakdown test using the QBD J-ramp test algorithm described in JESD35-A
"Procedure for Wafer-Level Testing of Thin Dielectrics," April 2011. This algorithm forces a
logarithmic current ramp until the oxide layer breaks down. This algorithm is capable of a maximum
current of ±1 A if a high power SMU is used. The flow diagram for the V-ramp test is shown in
flow diagram
See JEDEC standard JESD35-A "Procedure for Wafer-Level Testing of Thin Dielectrics," April 2011,
referenced in
Some of the descriptions of the following input variables and output variables are quoted from the
JESD35-A standard. The variables quoted from the standard include this reference identification:
(Ref. JESD35-A).
Notes on input variables
If there is no switching matrix in the system, input either 0 or -1 for hi_pin and lo_pins to bypass
switch.
I_init: For maximum sensitivity, the specified value should be well above the worst-case oxide
current of a "good" oxide and well above the system noise floor. Higher values must be specified for
ultra-thin oxide because of direct tunneling effects (Ref. JESD35-A).
4200A-901-01 Rev. C / February 2017
Voltage stress array
Measured current array
Time stamp array indicating when current is measured
Accumulated charge array
Charge-to-breakdown; cumulative charge (C) passing through the oxide before
breakdown (Ref. JESD35-A)
Charge-to-breakdown density (C/cm
Applied voltage at the step just before oxide breakdown (Ref. JESD35-A)
Measured current at v_bd, just before oxide breakdown
Time stamp when measuring I_bd
•
Initial test failure
•
Catastrophic failure (initial test pass, ramp test fail, post test fail)
•
Masked Catastrophic (initial test pass, ramp test pass, post test fail)
•
Non-Catastrophic (initial test pass, ramp test fail, post test pass)
•
Others (initial test pass, ramp test pass, post test pass)
See Details
(on page L-19).
Signatone CM500 Prober
2
) (Ref. JESD35-A)
(on page K-1).
Appendix L: Wafer-level reliability testing
J-ramp
L-17