Elastic And Transmitter Buffers; Receiver Buffer; Clock Correction; Figure 2-2: Clock Correction In Receiver - Xilinx RocketIO User Manual

Elastic and Transmitter Buffers

Elastic and Transmitter Buffers
Both the transmitter and the receiver include buffers (FIFOs) in the data path. This section
gives the reasons for including the buffers and outlines their operation.

Receiver Buffer

The receiver buffer is required for two reasons:
•
•
The receiver uses an elastic buffer, where "elastic" refers to the ability to modify the read
pointer for clock correction and channel bonding.

Clock Correction

Clock RXRECCLK (the recovered clock) reflects the data rate of the incoming data. Clock
RXUSRCLK defines the rate at which the FPGA core consumes the data. Ideally, these rates
are identical. However, since the clocks typically have different sources, one of the clocks is
faster than the other. The receiver buffer accommodates this difference between the clock
rates. See
Nominally, the buffer is always half full. This is shown in the top buffer,
the shaded area represents buffered data not yet read. Received data is inserted via the
write pointer under control of RXRECCLK. The FPGA core reads data via the read pointer
under control of RXUSRCLK. The half full/half empty condition of the buffer gives a
cushion for the differing clock rates. This operation continues indefinitely, regardless of
whether or not "meaningful" data is being received. When there is no meaningful data to
be received, the incoming data consists of IDLE characters or other padding.
If RXUSRCLK is faster than RXRECCLK, the buffer becomes more empty over time. The
clock correction logic corrects for this by decrementing the read pointer to reread a
repeatable byte sequence. This is shown in the middle buffer,
read pointer decrements to the value represented by the dashed pointer. By decrementing
the read pointer instead of incrementing it in the usual fashion, the buffer is partially
refilled. The transceiver inserts a single repeatable byte sequence when necessary to refill a
buffer. If the byte sequence length is greater than one, and if attribute
CLK_COR_REPEAT_WAIT is 0, then the transceiver can repeat the same sequence
multiple times until the buffer is refilled to the half-full condition.
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide
To accommodate the slight difference in frequency between the recovered clock
RXRECCLK and the internal FPGA core clock RXUSRCLK (clock correction)
To allow realignment of the input stream to ensure proper alignment of data being
read through multiple transceivers (channel bonding)
Figure 2-2.
Read
RXUSRCLK
Read
Removable sequence

Figure 2-2: Clock Correction in Receiver

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RXRECCLK
"Nominal" condition: buffer half-full
Read Write
Buffer less than half -full (emptying)
Repeatable sequence
Buffer more than half-full (filling up)
Figure 2-2, where
Write
Write
DS083-2_15_100901
Figure 2-2, where the solid
R
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