After Power-Up And Configuration; After Turning On A Reference Clock To The Tx Pll; After Changing The Reference Clock To The Tx Pll; After Assertion/Deassertion Of Txpowerdown - Xilinx Virtex-6 FPGA User Manual

Chapter 3: Transmitter
See

After Power-up and Configuration

The entire GTX TX is reset automatically after configuration-provided
TXPLLPOWERDOWN is Low. The supplies for the calibration resistor and calibration
resistor reference must be powered up before configuration to ensure correct calibration of
the termination impedance of all transceivers.

After Turning on a Reference Clock to the TX PLL

The reference clock source(s) and the power to the GTX transceiver(s) must be available
before configuring the FPGA. The reference clock must be stable before configuration
especially when using PLL-based clock sources (e.g., voltage controlled crystal oscillators).
If the reference clock(s) changes or GTX transceiver(s) are powered up after configuration,
GTXTXRESET is asserted to allow the TX PLL(s) to lock.

After Changing the Reference Clock to the TX PLL

Whenever the reference clock input to the TX PLL is changed, the TX PLL must be reset
afterwards to ensure that it locks to the new frequency. The GTXTXRESET port must be
used for this purpose. Refer to

After Assertion/Deassertion of TXPOWERDOWN

After the TXPOWERDOWN signal is deasserted, GTXTXRESET must be asserted.

TX Rate Change with the TX Buffer Enabled

After TXRATEDONE is asserted, indicating the rate change has completed, the TX PLL
output clock dividers must be reset followed by a TX PCS reset. To reset the clock dividers,
GTXTEST[1] is asserted for at least 16 TXUSRCLK2 cycles. To reset the TX PCS, TXRESET
is asserted.
To automatically reset the TX buffer after the rate change, the TX_EN_RATE_RESET_BUF
attribute is set to "TRUE."

TX Rate Change with the TX Buffer Bypassed

After TXRATEDONE is asserted, indicating the rate change has completed, the TX PLL
output clock dividers must be reset. Phase alignment must be performed again followed
by reset of the TX PCS. See
procedure.

TX Parallel Clock Source Reset

The clocks driving TXUSRCLK and TXUSRCLK2 must be stable for correct operation.
These clocks are often driven from an MMCM in the FPGA to meet phase and frequency
requirements. If the MMCM loses lock and begins producing incorrect output, TXRESET
must be used to hold TX PCS in reset until the clock source is locked again.
If the TX buffer is bypassed and phase alignment is in use, phase alignment must be
performed again after the clock source relocks.
www.BDTIC.com/XILINX
142
TX Buffer Bypass, page 155
TX Buffer Bypass, page 155
www.xilinx.com
for details on the rate change procedure.
Reference Clock Selection, page 102
for details on the rate change
Virtex-6 FPGA GTX Transceivers User Guide
for more details.
UG366 (v2.5) January 17, 2011