Description; Using The Tx Buffer; Using The Tx Phase-Alignment Circuit To Bypass The Tx Buffer - Xilinx Virtex-5 RocketIO GTP User Manual

Chapter 6: GTP Transmitter (TX)

Description

Using the TX Buffer

To use the TX buffer to resolve phase differences between the domains, TX_BUFFER_USE
must be set to TRUE. The buffer should be reset whenever TXBUFSTATUS indicates an
overflow or an underflow. The buffer can be reset using GTPRESET (see
or TXRESET (see
sequence that resets the entire GTP_DUAL tile.

Using the TX Phase-Alignment Circuit to Bypass the TX Buffer

If TX_BUFFER_USE is set to FALSE, the TX phase-alignment circuit must be used instead.
To use the phase-alignment circuit to force the XCLK phase to match the TXUSRCLK
phase, follow these steps:
1.
2.
3.
4.
5.
Table 6-9: Number of Required TXUSRCLK2 Clock Cycles
The phase-alignment procedure must be redone if any of the following conditions occur:
•
•
•
Figure 6-12
TXPMASETPHASE are shared tile pins (see
procedure is always applied to both GTP transceivers on the tile. TXOUTCLK cannot be
the source for TXUSRCLK when the TX phase-alignment circuit is used. See
Interface," page 90
106
"FPGA TX Interface," page
Set TXRX_INVERT0 and TXRX_INVERT1 to 00100.
Set TX_XCLK_SEL0 and TX_XCLK_SEL1 to "TXUSR".
Wait for all clocks to stabilize, then drive TXENPMAPHASEALIGN High. Keep
TXENPMAPHASEALIGN High unless the phase-alignment procedure must be
repeated. Driving TXENPMAPHASEALIGN Low will cause phase alignment to be
lost.
Wait 32 TXUSRCLK2 clock cycles, then drive TXPMASETPHASE High.
Wait the number of required TXUSRCLK2 clock cycles as specified in
drive TXPMASETPHASE Low. The phase of the PMACLK is now aligned with
TXUSRCLK.
PLL_DIVSEL_COMM_OUT
PLL_DIVSEL_OUT_0
PLL_DIVSEL_OUT_1
1
2
3
GTPRESET is asserted
PLLPOWERDWNB is deasserted
The clocking source changed
shows the TX phase-alignment procedure. TXENPMAPHASEALIGN and
for details.
www.xilinx.com
90). Assertion of GTPRESET triggers a
TXUSRCLK2 Wait Cycles
4096
8192
16384
"Shared PMA PLL," page
Virtex-5 RocketIO GTP Transceiver User Guide
R
"Reset," page 72)
Table 6-9, then
60), so the
"FPGA TX
UG196 (v1.3) May 25, 2007