(Syscfg_Exticr4); Compensation Cell Control Register (Syscfg_Cmpcr) - ST STM32F205 series Reference Manual

System configuration controller (SYSCFG)
Bits 31:16
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 8 to 11)
7.2.6 SYSCFG external interrupt configuration register 4

(SYSCFG_EXTICR4)

Address offset: 0x14
Reset value: 0x0000
31 30 29
15 14 13
EXTI15[3:0]
rw rw rw
Bits 31:16 Reserved
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 12 to 15)
These bits are written by software to select the source input for the EXTIx external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
0111: PH[x] pin
Note: PI[15:12] are not used.
7.2.7

Compensation cell control register (SYSCFG_CMPCR)

Address offset: 0x20
Reset value: 0x0000 0000
31 30 29
15 14 13
Reserved
162/1378
Reserved
These bits are written by software to select the source input for the EXTIx external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
0111: PH[x] pin
1000: PI[x] pin
28 27 26 25
12 11 10 9
EXTI14[3:0]
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28 27 26 25
12 11 10 9
24 23 22
Reserved
8 7 6
EXTI13[3:0]
rw rw rw
24 23 22
Reserved
8 7 6
READY
r
RM0033 Rev 8
21 20 19 18
5 4 3 2
EXTI12[3:0]
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21 20 19 18
5 4 3 2
Reserved
RM0033
17 16
1 0
rw rw
17 16
1 0
CMP_
PD
rw