Compensation Cell Control Register (Syscfg_Cmpcr); Syscfg Configuration Register (Syscfg_Cfgr) - ST STM32F446 Series Reference Manual

Advanced arm-based 32-bit mcus

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System configuration controller (SYSCFG)

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 12 to 15)

Compensation cell control register (SYSCFG_CMPCR)

Address offset: 0x20

Reset value: 0x0000 0000

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 READY: Compensation cell ready flag

Bits 7:1 Reserved, must be kept at reset value.

Bit 0 CMP_PD: Compensation cell power-down

Address offset: 0x2C

Reset value: 0x0000 0000

These bits are written by software to select the source input for the EXTIx external

Note: 0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

0101: PF[x] pin

0110: PG[x] pin

0: I/O compensation cell not ready

1: O compensation cell ready

0: I/O compensation cell power-down mode

1: I/O compensation cell enabled

RM0390 Rev 4

FMPI2C1_SDA FMPI2C1_SCL

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