Rcc Ahb2 Peripheral Clock Enable Register (Rcc_Ahb2Enr) - ST STM32F446 Series Reference Manual

RM0390
Bit 7 GPIOHEN: IO port H clock enable
This bit is set and cleared by software.
0: IO port H clock disabled
1: IO port H clock enabled
Bit 6 GPIOGEN: IO port G clock enable
This bit is set and cleared by software.
0: IO port G clock disabled
1: IO port G clock enabled
Bit 5 GPIOFEN: IO port F clock enable
This bit is set and cleared by software.
0: IO port F clock disabled
1: IO port F clock enabled
Bit 4 GPIOEEN: IO port E clock enable
This bit is set and cleared by software.
0: IO port E clock disabled
1: IO port E clock enabled
Bit 3 GPIODEN: IO port D clock enable
This bit is set and cleared by software.
0: IO port D clock disabled
1: IO port D clock enabled
Bit 2 GPIOCEN: IO port C clock enable
This bit is set and cleared by software.
0: IO port C clock disabled
1: IO port C clock enabled
Bit 1 GPIOBEN: IO port B clock enable
This bit is set and cleared by software.
0: IO port B clock disabled
1: IO port B clock enabled
Bit 0 GPIOAEN: IO port A clock enable
This bit is set and cleared by software.
0: IO port A clock disabled
1: IO port A clock enabled
6.3.11

RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)

Address offset: 0x34
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
Res. Res. Res. Res.
RM0390 Rev 4
23 22 21
Res. Res. Res.
7 6 5
OTGFSEN Res. Res.
rw
Reset and clock control (RCC)
20 19 18 17
Res. Res. Res. Res.
4 3 2
Res. Res. Res. Res.
16
Res.
1 0
DCMIEN
rw
145/1328
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