Rcc Ahb2 Peripheral Clock Enable Register (Rcc_Ahb2Enr) - ST STM32F207 Series Reference Manual

Reset and clock control (RCC)
Bit 1 GPIOBEN: IO port B clock enable
Set and cleared by software.
0: IO port B clock disabled
1: IO port B clock enabled
Bit 0 GPIOAEN: IO port A clock enable
Set and cleared by software.
0: IO port A clock disabled
1: IO port A clock enabled
5.3.11

RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)

Address offset: 0x34
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29
15 14 13
Bits 31:8 Reserved, always read as 0.
Bit 7 OTGFSEN: USB OTG FS clock enable
Set and cleared by software.
0: USB OTG FS clock disabled
1: USB OTG FS clock enabled
Bit 6 RNGEN: Random number generator clock enable
Set and cleared by software.
0: Random number generator clock disabled
1: Random number generator clock enabled
Bit 5 HASHEN: Hash modules clock enable
Set and cleared by software.
0: Hash modules clock disabled
1: Hash modules clock enabled
Bit 4 CRYPEN: Cryptographic modules clock enable
Set and cleared by software.
0: cryptographic module clock disabled
1: cryptographic module clock enabled
Bit 3:1 Reserved, always read as 0
Bit 0 DCMIEN: Camera interface enable
Set and cleared by software.
0: Camera interface clock disabled
1: Camera interface clock enabled
114/1381
28 27 26 25
12 11 10 9
Reserved
24 23 22
Reserved
8 7 6
OTGFS RNG HASH
EN EN
rw rw
RM0033 Rev 9
21 20 19 18
5 4 3 2
CRYP
EN EN
Reserved
rw rw
RM0033
17 16
1 0
DCMI
EN
rw