Rcc Ahb2 Peripheral Clock Enable Register (Rcc_Ahb2Enr) - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution

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RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)

Address offset: 0x04C

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

When the peripheral clock is not active, the peripheral registers read or write access from

CPU1 is not supported.

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 GPIOHEN: CPU1 IO port H clock enable

This bit is set and cleared by software.

0: IO port H clock disabled for CPU1

1: IO port H clock enabled for CPU1

Bits 6:3 Reserved, must be kept at reset value.

Bit 2 GPIOCEN: CPU1 IO port C clock enable

This bit is set and cleared by software.

0: IO port C clock disabled for CPU1

1: IO port C clock enabled for CPU1

Bit 1 GPIOBEN: CPU1 IO port B clock enable

This bit is set and cleared by software.

0: IO port B clock disabled for CPU1

1: IO port B clock enabled for CPU1

Bit 0 GPIOAEN: CPU1 IO port A clock enable

This bit is set and cleared by software.

0: IO port A clock disabled for CPU1

1: IO port A clock enabled for CPU1

RM0453 Rev 1

Reset and clock control (RCC)

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