Serial Status Register (Ssr) - Fujitsu F2MC-16LX Hardware Manual

17.3.4 Serial Status Register (SSR)

The serial status register (SSR) is comprised of flags that represent the UART
operating status.
■ Serial Status Register (SSR)
Figure 17.3-5 Configuration of Serial Status Register (SSR)
Serial status register
Address:000023
Read/write
Initial value
[bit15] PE (Parity error)
The PE bit is an interrupt request flag that is set when a parity error occurs during the
receive operation. To clear the flag set once, write "0" into the REC bit (bit10) of the SCR
register.
If the bit is set, data in the SIDR register becomes invalid.
Table 17.3-12 Function of PE (Parity Error) Bit
PE
0
1
[bit14] ORE (Over run error)
The ORE bit is an interrupt request flag that is set when an overrun error occurs during the
receive operation. To clear the flag set once, write "0" into the REC bit (bit10) of the SCR
register.
If the bit is set, data in the SIDR register becomes invalid.
Table 17.3-13 Function of ORE (Over Run Error)
ORE
0
1
[bit13] FRE (Framing error)
The FRE bit is an interrupt request flag that is set when a framing error occurs during the
receive operation. To clear the flag set once, write "0" into the REC bit (bit10) of the SCR
register. If the bit is set, data in the SIDR register becomes invalid.
15 14 13
bit
PE ORE FRE
H
(R/W) (R/W) (R/W) (R/W) (R/W)
(0) (0) (0)
No parity error [Initial value]
Parity error occurs.
No overrun error [Initial value]
Overrun error occurs.
12 11 10 9
RDRF TDRE RIE
(-) (R/W) (R/W)
(0) (1) (-) (0)
Function
Function
17.3 UART Registers
8
TIE SSR
(0)
267