Serial Status Register 0 To 3 (Ssr0 To Ssr3) - Fujitsu F2MC-16LX Hardware Manual

21.4.3

Serial Status Register 0 to 3 (SSR0 to SSR3)

The serial status registers 0 to 3 (SSR0 to SSR3) are responsible for checking sending
and receiving and the states of errors, and setting interrupts to be enabled or disabled.
Serial Status Register 0 to 3 (SSR0 to SSR3)
Address
ch0 : 000023
H
ch1 : 000029
H
ch2 : 00002F
H
ch3 : 000035
H
R/W : Readable/Writable
R : Read only
: Initial value
Figure 21.4-4 Serial Status Register 0 to 3 (SSR0 to SSR3)
bit15 bit14 bit13 bit12 bit11 bit10
ORE FRE RDRF TDRE BDS
PE
R
R R
R
bit9 bit8 bit7
(SIDR0 to SIDR3,
RIE TIE
R/W
R R/W R/W
TIE Transfer interrupt request enable bit
0 Transfer interrupt request output disabled
Transfer interrupt request output enabled
1
RIE
Receive interrupt request enable bit
0
Receive interrupt request output disabled
Receive interrupt request output enabled
1
BDS
Transfer dirction selection bit
LSB first (Transfer form Least significant bit)
0
1 MSB first (Transfer form Most significant bit)
Transfer data empty flag bit
TDRE
0
With Transfer data (Transfer data writing disabled)
1
No Transfer data (Transfer data writing enabled)
Receive data full flag bit
RDRF
No Receive data
0
1 With Receive data
Framing error flag bit
FRE
0
No Framing error
1
With Framing error
Over run error flag bit
ORE
No Over run error
0
With Over run error
1
PE Parity error flag bit
0
No Parity error
With Parity error
1
CHAPTER 21 UART
bit0
Initial vlaue
00001000
SODR0 to SODR3)
B
487