Fujitsu FR Family Manuals

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Fujitsu FR Family Instruction Manual

Fujitsu FR Family Instruction Manual (314 pages)

Brand: Fujitsu | Category: Printer Accessories | Size: 5.6 MB
Table of contents
Table Of Contents9................................................................................................................................................................
Chapter 1 Fr Family Overview25................................................................................................................................................................
Features Of The Fr Family Cpu Core26................................................................................................................................................................
Sample Configuration Of An Fr Family Device27................................................................................................................................................................
Sample Configuration Of The Fr Family Cpu28................................................................................................................................................................
Chapter 2 Memory Architecture29................................................................................................................................................................
Fr Family Memory Space30................................................................................................................................................................
Unused Vector Table Area30................................................................................................................................................................
Direct Address Area31................................................................................................................................................................
Vector Table Area32................................................................................................................................................................
Overview Of Vector Table Areas32................................................................................................................................................................
Contents Of Vector Table Areas33................................................................................................................................................................
Vector Table Area Initial Value33................................................................................................................................................................
Bit Order And Byte Order34................................................................................................................................................................
Word Alignment35................................................................................................................................................................
Program Restrictions On Word Alignment35................................................................................................................................................................
Data Restrictions On Word Alignment35................................................................................................................................................................
Chapter 3 Register Descriptions37................................................................................................................................................................
Fr Family Register Configuration38................................................................................................................................................................
General-purpose Registers39................................................................................................................................................................
Dedicated Registers41................................................................................................................................................................
Program Counter (pc)42................................................................................................................................................................
Program Status (ps)43................................................................................................................................................................
Table Base Register (tbr)47................................................................................................................................................................
Overview Of The Table Base Register47................................................................................................................................................................
Table Base Register Configuration48................................................................................................................................................................
Table Base Register Functions48................................................................................................................................................................
Precautions Related To The Table Base Register48................................................................................................................................................................
Return Pointer (rp)49................................................................................................................................................................
System Stack Pointer (ssp), User Stack Pointer (usp)51................................................................................................................................................................
Multiplication/division Register (md)53................................................................................................................................................................
Chapter 4 Reset And "eit" Processing55................................................................................................................................................................
Reset Processing57................................................................................................................................................................
Basic Operations In "eit" Processing58................................................................................................................................................................
Vector Table Configuration59................................................................................................................................................................
Interrupts61................................................................................................................................................................
User Interrupts62................................................................................................................................................................
Overview Of User Interrupts62................................................................................................................................................................
Conditions For Acceptance Of User Interrupt Requests62................................................................................................................................................................
How To Use User Interrupts63................................................................................................................................................................
Non-maskable Interrupts (nmi)64................................................................................................................................................................
Exception Processing66................................................................................................................................................................
Undefined Instruction Exceptions67................................................................................................................................................................
Traps68................................................................................................................................................................
Overview Of Traps68................................................................................................................................................................
Sources Of Traps68................................................................................................................................................................
Int" Instructions69................................................................................................................................................................
Inte" Instruction70................................................................................................................................................................
Step Trace Traps71................................................................................................................................................................
Overview Of Step Trace Traps71................................................................................................................................................................
Conditions For Generation Of Step Trace Traps71................................................................................................................................................................
Step Trace Trap Operation71................................................................................................................................................................
Pc" Values Saved For Step Trace Traps71................................................................................................................................................................
Precautionary Information For Use Of Step Trace Traps71................................................................................................................................................................
Coprocessor Not Found Traps72................................................................................................................................................................
Overview Of Coprocessor Not Found Traps72................................................................................................................................................................
Coprocessor Not Found Trap Operation72................................................................................................................................................................
Pc" Values Saved For Coprocessor Not Present Traps72................................................................................................................................................................
Coprocessor Error Trap73................................................................................................................................................................
Overview Of Coprocessor Error Traps73................................................................................................................................................................
Conditions For Generation Of Coprocessor Error Traps73................................................................................................................................................................
Coprocessor Error Trap Operation73................................................................................................................................................................
Pc" Values Saved For Coprocessor Error Traps73................................................................................................................................................................
Priority Levels75................................................................................................................................................................
Chapter 5 Precautionary Information For The Fr Family Cpu77................................................................................................................................................................
Pipeline Operation78................................................................................................................................................................
Pipeline Operation And Interrupt Processing79................................................................................................................................................................
Register Hazards80................................................................................................................................................................
Delayed Branching Processing82................................................................................................................................................................
Processing Non-delayed Branching Instructions84................................................................................................................................................................
Processing Delayed Branching Instructions85................................................................................................................................................................
Chapter 6 Instruction Overview87................................................................................................................................................................
Instruction Formats88................................................................................................................................................................
Instruction Notation Formats90................................................................................................................................................................
Chapter 7 Detailed Execution Instructions92................................................................................................................................................................
Add (add Word Data Of Source Register To Destination Register)96................................................................................................................................................................
Add (add 4-bit Immediate Data To Destination Register)97................................................................................................................................................................
Add2 (add 4-bit Immediate Data To Destination Register)98................................................................................................................................................................
Addc (add Word Data Of Source Register And Carry Bit To Destination Register)99................................................................................................................................................................
Addn (add Word Data Of Source Register To Destination Register)100................................................................................................................................................................
Addn (add Immediate Data To Destination Register)101................................................................................................................................................................
Addn2 (add Immediate Data To Destination Register)102................................................................................................................................................................
Sub (subtract Word Data In Source Register From Destination Register)103................................................................................................................................................................
Subc (subtract Word Data In Source Register And Carry Bit From Destination Register)104................................................................................................................................................................
Subc (subtract Word Data In Source Register And Carry Bit From Destination)104................................................................................................................................................................
Subn (subtract Word Data In Source Register From Destination Register)105................................................................................................................................................................
Cmp (compare Word Data In Source Register And Destination Register)106................................................................................................................................................................
Cmp (compare Immediate Data Of Source Register And Destination Register)107................................................................................................................................................................
Cmp2 (compare Immediate Data And Destination Register)108................................................................................................................................................................
And (and Word Data Of Source Register To Destination Register)109................................................................................................................................................................
And (and Word Data Of Source Register To Data In Memory)110................................................................................................................................................................
Andh (and Half-word Data Of Source Register To Data In Memory)112................................................................................................................................................................
Andb (and Byte Data Of Source Register To Data In Memory)114................................................................................................................................................................
Or (or Word Data Of Source Register To Destination Register)116................................................................................................................................................................
Or (or Word Data Of Source Register To Data In Memory)117................................................................................................................................................................
Orh (or Half-word Data Of Source Register To Data In Memory)119................................................................................................................................................................
Orb (or Byte Data Of Source Register To Data In Memory)121................................................................................................................................................................
Eor (exclusive Or Word Data Of Source Register To Destination Register)123................................................................................................................................................................
Eor (exclusive Or Word Data Of Source Register To Data In Memory)124................................................................................................................................................................
Eorh (exclusive Or Half-word Data Of Source Register To Data In Memory)126................................................................................................................................................................
Eorb (exclusive Or Byte Data Of Source Register To Data In Memory)128................................................................................................................................................................
Bandl (and 4-bit Immediate Data To Lower 4 Bits Of Byte Data In Memory)130................................................................................................................................................................
Bandh (and 4-bit Immediate Data To Higher 4 Bits Of Byte Data In Memory)132................................................................................................................................................................
Borl (or 4-bit Immediate Data To Lower 4 Bits Of Byte Data In Memory)134................................................................................................................................................................
Borh (or 4-bit Immediate Data To Higher 4 Bits Of Byte Data In Memory)136................................................................................................................................................................
Beorl (eor 4-bit Immediate Data To Lower 4 Bits Of Byte Data In Memory)138................................................................................................................................................................
Beorh (eor 4-bit Immediate Data To Higher 4 Bits Of Byte Data In Memory)140................................................................................................................................................................
Btstl (test Lower 4 Bits Of Byte Data In Memory)142................................................................................................................................................................
Btsth (test Higher 4 Bits Of Byte Data In Memory)143................................................................................................................................................................
Mul (multiply Word Data)144................................................................................................................................................................
Mulu (multiply Unsigned Word Data)146................................................................................................................................................................
Mulh (multiply Half-word Data)148................................................................................................................................................................
Muluh (multiply Unsigned Half-word Data)150................................................................................................................................................................
Div0s (initial Setting Up For Signed Division)152................................................................................................................................................................
Div0u (initial Setting Up For Unsigned Division)154................................................................................................................................................................
Div1 (main Process Of Division)156................................................................................................................................................................
Div2 (correction When Remainder Is 0)158................................................................................................................................................................
Div2 (correction When Remainder Is)158................................................................................................................................................................
Div3 (correction When Remainder Is 0)160................................................................................................................................................................
Div3 (correction When Remainder Is)160................................................................................................................................................................
Div4s (correction Answer For Signed Division)161................................................................................................................................................................
Lsl (logical Shift To The Left Direction)162................................................................................................................................................................
Lsl2 (logical Shift To The Left Direction)164................................................................................................................................................................
Lsr (logical Shift To The Right Direction)165................................................................................................................................................................
Lsr2 (logical Shift To The Right Direction)167................................................................................................................................................................
Asr (arithmetic Shift To The Right Direction)168................................................................................................................................................................
Asr2 (arithmetic Shift To The Right Direction)170................................................................................................................................................................
Ldi:32 (load Immediate 32-bit Data To Destination Register)171................................................................................................................................................................
Ldi:20 (load Immediate 20-bit Data To Destination Register)172................................................................................................................................................................
Ldi:8 (load Immediate 8-bit Data To Destination Register)173................................................................................................................................................................
Ld (load Word Data In Memory To Register)174................................................................................................................................................................
Ld (load Word Data In Memory To Program Status Register)181................................................................................................................................................................
Lduh (load Half-word Data In Memory To Register)183................................................................................................................................................................
Ldub (load Byte Data In Memory To Register)186................................................................................................................................................................
St (store Word Data In Register To Memory)189................................................................................................................................................................
St (store Word Data In Program Status Register To Memory)195................................................................................................................................................................
Sth (store Half-word Data In Register To Memory)196................................................................................................................................................................
Stb (store Byte Data In Register To Memory)199................................................................................................................................................................
Mov (move Word Data In Source Register To Destination Register)202................................................................................................................................................................
Mov (move Word Data In Program Status Register To Destination Register)204................................................................................................................................................................
Mov (move Word Data In Source Register To Program Status Register)206................................................................................................................................................................
Jmp (jump)208................................................................................................................................................................
Call (call Subroutine)209................................................................................................................................................................
Ret (return From Subroutine)211................................................................................................................................................................
Int (software Interrupt)212................................................................................................................................................................
Inte (software Interrupt For Emulator)214................................................................................................................................................................
Reti (return From Interrupt)216................................................................................................................................................................
Bcc (branch Relative If Condition Satisfied)218................................................................................................................................................................
Jmp:d (jump)220................................................................................................................................................................
Call:d (call Subroutine)221................................................................................................................................................................
Ret:d (return From Subroutine)225................................................................................................................................................................
Bcc:d (branch Relative If Condition Satisfied)227................................................................................................................................................................
Dmov (move Word Data From Direct Address To Register)229................................................................................................................................................................
Dmov (move Word Data From Register To Direct Address)230................................................................................................................................................................
Dmovh (move Half-word Data From Direct Address To Register)239................................................................................................................................................................
Dmovh (move Half-word Data From Register To Direct Address)240................................................................................................................................................................
Dmovb (move Byte Data From Direct Address To Register)245................................................................................................................................................................
Dmovb (move Byte Data From Register To Direct Address)246................................................................................................................................................................
Ldres (load Word Data In Memory To Resource)251................................................................................................................................................................
Stres (store Word Data In Resource To Memory)252................................................................................................................................................................
Copop (coprocessor Operation)253................................................................................................................................................................
Copld (load 32-bit Data From Register To Coprocessor Register)255................................................................................................................................................................
Copst (store 32-bit Data From Coprocessor Register To Register)257................................................................................................................................................................
Copsv (save 32-bit Data From Coprocessor Register To Register)259................................................................................................................................................................
Nop (no Operation)261................................................................................................................................................................
Andccr (and Condition Code Register And Immediate Data)262................................................................................................................................................................
Orccr (or Condition Code Register And Immediate Data)263................................................................................................................................................................
Stilm (set Immediate Data To Interrupt Level Mask Register)264................................................................................................................................................................
Addsp (add Stack Pointer And Immediate Data)265................................................................................................................................................................
Extsb (sign Extend From Byte Data To Word Data)266................................................................................................................................................................
Extub (unsign Extend From Byte Data To Word Data)267................................................................................................................................................................
Extsh (sign Extend From Byte Data To Word Data)268................................................................................................................................................................
Extuh (unsigned Extend From Byte Data To Word Data)269................................................................................................................................................................
Ldm0 (load Multiple Registers)270................................................................................................................................................................
Ldm1 (load Multiple Registers)272................................................................................................................................................................
Stm0 (store Multiple Registers)274................................................................................................................................................................
Stm1 (store Multiple Registers)276................................................................................................................................................................
Enter (enter Function)278................................................................................................................................................................
Leave (leave Function)280................................................................................................................................................................
Xchb (exchange Byte Data)282................................................................................................................................................................
Appendix285................................................................................................................................................................
Appendix A Instruction Lists286................................................................................................................................................................
A.1 Symbols Used In Instruction Lists287................................................................................................................................................................
A.2 Instruction Lists289................................................................................................................................................................
Appendix B Instruction Maps298................................................................................................................................................................
B.1 Instruction Map299................................................................................................................................................................
B.2 "e" Format300................................................................................................................................................................
Index301................................................................................................................................................................

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Fujitsu FR Family Instruction Manual

Fujitsu FR Family Instruction Manual (304 pages)

32-BIT MICROCONTROLLER  
Brand: Fujitsu | Category: Control Units | Size: 6.31 MB
Table of contents
Table Of Contents9................................................................................................................................................................
Chapter 1 Fr Family Overview17................................................................................................................................................................
Features Of The Fr Family Cpu Core18................................................................................................................................................................
Sample Configuration Of An Fr Family Device19................................................................................................................................................................
Sample Configuration Of The Fr Family Cpu20................................................................................................................................................................
Chapter 2 Memory Architecture21................................................................................................................................................................
Fr Family Memory Space22................................................................................................................................................................
Direct Address Area23................................................................................................................................................................
Use Of Operand Information Contained In Instructions23................................................................................................................................................................
Vector Table Area24................................................................................................................................................................
Bit Order And Byte Order26................................................................................................................................................................
Word Alignment27................................................................................................................................................................
Chapter 3 Register Descriptions29................................................................................................................................................................
Fr Family Register Configuration30................................................................................................................................................................
General-purpose Registers31................................................................................................................................................................
Dedicated Registers33................................................................................................................................................................
Program Counter (pc)34................................................................................................................................................................
Program Status (ps)35................................................................................................................................................................
Table Base Register (tbr)39................................................................................................................................................................
Return Pointer (rp)41................................................................................................................................................................
System Stack Pointer (ssp), User Stack Pointer (usp)43................................................................................................................................................................
Multiplication/division Register (md)45................................................................................................................................................................
Chapter 4 Reset And "eit" Processing47................................................................................................................................................................
Reset Processing49................................................................................................................................................................
Basic Operations In "eit" Processing50................................................................................................................................................................
Interrupts53................................................................................................................................................................
Overview Of Interrupt Processing53................................................................................................................................................................
Sources Of Interrupts53................................................................................................................................................................
External Interrupts54................................................................................................................................................................
Overview Of External Interrupts54................................................................................................................................................................
Time To Start Of Interrupt Processing55................................................................................................................................................................
Pc" Values Saved For Interrupts55................................................................................................................................................................
Non-maskable Interrupts (nmi)56................................................................................................................................................................
Overview Of Non-maskable Interrupts56................................................................................................................................................................
Time To Start Of Non-maskable Interrupt Processing56................................................................................................................................................................
Pc" Values Saved For Non-maskable Interrupts57................................................................................................................................................................
How To Use Non-maskable Interrupts57................................................................................................................................................................
Exception Processing58................................................................................................................................................................
Undefined Instruction Exceptions59................................................................................................................................................................
Undefined Instructions Placed In Delay Slots59................................................................................................................................................................
Traps60................................................................................................................................................................
Int" Instructions61................................................................................................................................................................
Overview Of The "int" Instruction61................................................................................................................................................................
Int" Instruction Operation61................................................................................................................................................................
Inte" Instruction62................................................................................................................................................................
Overview Of The "inte" Instruction62................................................................................................................................................................
Inte" Instruction Operation62................................................................................................................................................................
Step Trace Traps63................................................................................................................................................................
Coprocessor Not Found Traps64................................................................................................................................................................
Coprocessor Error Trap65................................................................................................................................................................
Priority Levels67................................................................................................................................................................
Chapter 5 Precautionary Information For The Fr Family Cpu69................................................................................................................................................................
Pipeline Operation70................................................................................................................................................................
Pipeline Operation And Interrupt Processing71................................................................................................................................................................
Register Hazards72................................................................................................................................................................
Delayed Branching Processing74................................................................................................................................................................
Instructions Prohibited In Delay Slots74................................................................................................................................................................
Processing Non-delayed Branching Instructions76................................................................................................................................................................
Processing Delayed Branching Instructions77................................................................................................................................................................
Chapter 6 Instruction Overview79................................................................................................................................................................
Instruction Formats80................................................................................................................................................................
Instruction Notation Formats82................................................................................................................................................................
Chapter 7 Detailed Execution Instructions84................................................................................................................................................................
Add (add Word Data Of Source Register To Destination Register)88................................................................................................................................................................
Add (add 4-bit Immediate Data To Destination Register)89................................................................................................................................................................
Add2 (add 4-bit Immediate Data To Destination Register)90................................................................................................................................................................
Addc (add Word Data Of Source Register And Carry Bit To Destination Register)91................................................................................................................................................................
Addn (add Word Data Of Source Register To Destination Register)92................................................................................................................................................................
Addn (add Immediate Data To Destination Register)93................................................................................................................................................................
Addn2 (add Immediate Data To Destination Register)94................................................................................................................................................................
Sub (subtract Word Data In Source Register From Destination Register)95................................................................................................................................................................
Subc (subtract Word Data In Source Register And Carry Bit From Destination Register)96................................................................................................................................................................
Subc (subtract Word Data In Source Register And Carry Bit From Destination)96................................................................................................................................................................
Subn (subtract Word Data In Source Register From Destination Register)97................................................................................................................................................................
Cmp (compare Word Data In Source Register And Destination Register)98................................................................................................................................................................
Cmp (compare Immediate Data Of Source Register And Destination Register)99................................................................................................................................................................
Cmp2 (compare Immediate Data And Destination Register)100................................................................................................................................................................
And (and Word Data Of Source Register To Destination Register)101................................................................................................................................................................
And (and Word Data Of Source Register To Data In Memory)102................................................................................................................................................................
Andh (and Half-word Data Of Source Register To Data In Memory)104................................................................................................................................................................
Andb (and Byte Data Of Source Register To Data In Memory)106................................................................................................................................................................
Or (or Word Data Of Source Register To Destination Register)108................................................................................................................................................................
Or (or Word Data Of Source Register To Data In Memory)109................................................................................................................................................................
Orh (or Half-word Data Of Source Register To Data In Memory)111................................................................................................................................................................
Orb (or Byte Data Of Source Register To Data In Memory)113................................................................................................................................................................
Eor (exclusive Or Word Data Of Source Register To Destination Register)115................................................................................................................................................................
Eor (exclusive Or Word Data Of Source Register To Data In Memory)116................................................................................................................................................................
Eorh (exclusive Or Half-word Data Of Source Register To Data In Memory)118................................................................................................................................................................
Eorb (exclusive Or Byte Data Of Source Register To Data In Memory)120................................................................................................................................................................
Bandl (and 4-bit Immediate Data To Lower 4 Bits Of Byte Data In Memory)122................................................................................................................................................................
Bandh (and 4-bit Immediate Data To Higher 4 Bits Of Byte Data In Memory)124................................................................................................................................................................
Borl (or 4-bit Immediate Data To Lower 4 Bits Of Byte Data In Memory)126................................................................................................................................................................
Borh (or 4-bit Immediate Data To Higher 4 Bits Of Byte Data In Memory)128................................................................................................................................................................
Beorl (eor 4-bit Immediate Data To Lower 4 Bits Of Byte Data In Memory)130................................................................................................................................................................
Beorh (eor 4-bit Immediate Data To Higher 4 Bits Of Byte Data In Memory)132................................................................................................................................................................
Btstl (test Lower 4 Bits Of Byte Data In Memory)134................................................................................................................................................................
Btsth (test Higher 4 Bits Of Byte Data In Memory)135................................................................................................................................................................
Mul (multiply Word Data)136................................................................................................................................................................
Mulu (multiply Unsigned Word Data)138................................................................................................................................................................
Mulh (multiply Half-word Data)140................................................................................................................................................................
Muluh (multiply Unsigned Half-word Data)142................................................................................................................................................................
Div0s (initial Setting Up For Signed Division)144................................................................................................................................................................
Div0u (initial Setting Up For Unsigned Division)146................................................................................................................................................................
Div1 (main Process Of Division)148................................................................................................................................................................
Div2 (correction When Remainder Is 0)150................................................................................................................................................................
Div2 (correction When Remainder Is)150................................................................................................................................................................
Div3 (correction When Remainder Is 0)152................................................................................................................................................................
Div3 (correction When Remainder Is)152................................................................................................................................................................
Div4s (correction Answer For Signed Division)153................................................................................................................................................................
Lsl (logical Shift To The Left Direction)154................................................................................................................................................................
Lsl2 (logical Shift To The Left Direction)156................................................................................................................................................................
Lsr (logical Shift To The Right Direction)157................................................................................................................................................................
Lsr2 (logical Shift To The Right Direction)159................................................................................................................................................................
Asr (arithmetic Shift To The Right Direction)160................................................................................................................................................................
Asr2 (arithmetic Shift To The Right Direction)162................................................................................................................................................................
Ldi:32 (load Immediate 32-bit Data To Destination Register)163................................................................................................................................................................
Ldi:20 (load Immediate 20-bit Data To Destination Register)164................................................................................................................................................................
Ldi:8 (load Immediate 8-bit Data To Destination Register)165................................................................................................................................................................
Ld (load Word Data In Memory To Register)166................................................................................................................................................................
Ld (load Word Data In Memory To Program Status Register)173................................................................................................................................................................
Lduh (load Half-word Data In Memory To Register)175................................................................................................................................................................
Ldub (load Byte Data In Memory To Register)178................................................................................................................................................................
St (store Word Data In Register To Memory)181................................................................................................................................................................
St (store Word Data In Program Status Register To Memory)187................................................................................................................................................................
Sth (store Half-word Data In Register To Memory)188................................................................................................................................................................
Stb (store Byte Data In Register To Memory)191................................................................................................................................................................
Mov (move Word Data In Source Register To Destination Register)194................................................................................................................................................................
Mov (move Word Data In Program Status Register To Destination Register)196................................................................................................................................................................
Mov (move Word Data In Source Register To Program Status Register)198................................................................................................................................................................
Jmp (jump)199................................................................................................................................................................
Call (call Subroutine)200................................................................................................................................................................
Ret (return From Subroutine)202................................................................................................................................................................
Int (software Interrupt)203................................................................................................................................................................
Inte (software Interrupt For Emulator)205................................................................................................................................................................
Reti (return From Interrupt)207................................................................................................................................................................
Bcc (branch Relative If Condition Satisfied)209................................................................................................................................................................
Jmp:d (jump)211................................................................................................................................................................
Call:d (call Subroutine)212................................................................................................................................................................
Ret:d (return From Subroutine)215................................................................................................................................................................
Bcc:d (branch Relative If Condition Satisfied)216................................................................................................................................................................
Dmov (move Word Data From Direct Address To Register)218................................................................................................................................................................
Dmov (move Word Data From Register To Direct Address)219................................................................................................................................................................
Dmov (move Word Data From Direct Address To Post Increment Register Indirect Address)220................................................................................................................................................................
Dmov (move Word Data From Post Increment Register Indirect Address To Direct Address)222................................................................................................................................................................
Dmov (move Word Data From Direct Address To Pre-decrement Register Indirect Address)224................................................................................................................................................................
Dmovh (move Half-word Data From Direct Address To Register)228................................................................................................................................................................
Dmovh (move Half-word Data From Register To Direct Address)229................................................................................................................................................................
Dmovb (move Byte Data From Direct Address To Register)234................................................................................................................................................................
Dmovb (move Byte Data From Register To Direct Address)235................................................................................................................................................................
Dmovb (move Byte Data From Direct Address To Post Increment Register Indirect Address)236................................................................................................................................................................
Dmovb (move Byte Data From Post Increment Register Indirect Address To Direct Address)238................................................................................................................................................................
Ldres (load Word Data In Memory To Resource)240................................................................................................................................................................
Stres (store Word Data In Resource To Memory)241................................................................................................................................................................
Copop (coprocessor Operation)242................................................................................................................................................................
Copld (load 32-bit Data From Register To Coprocessor Register)244................................................................................................................................................................
Copst (store 32-bit Data From Coprocessor Register To Register)246................................................................................................................................................................
Copsv (save 32-bit Data From Coprocessor Register To Register)248................................................................................................................................................................
Nop (no Operation)250................................................................................................................................................................
Andccr (and Condition Code Register And Immediate Data)251................................................................................................................................................................
Orccr (or Condition Code Register And Immediate Data)252................................................................................................................................................................
Stilm (set Immediate Data To Interrupt Level Mask Register)253................................................................................................................................................................
Addsp (add Stack Pointer And Immediate Data)254................................................................................................................................................................
Extsb (sign Extend From Byte Data To Word Data)255................................................................................................................................................................
Extub (unsign Extend From Byte Data To Word Data)256................................................................................................................................................................
Extsh (sign Extend From Byte Data To Word Data)257................................................................................................................................................................
Extuh (unsigned Extend From Byte Data To Word Data)258................................................................................................................................................................
Ldm0 (load Multiple Registers)259................................................................................................................................................................
Ldm1 (load Multiple Registers)261................................................................................................................................................................
Stm0 (store Multiple Registers)263................................................................................................................................................................
Stm1 (store Multiple Registers)265................................................................................................................................................................
Enter (enter Function)267................................................................................................................................................................
Leave (leave Function)269................................................................................................................................................................
Xchb (exchange Byte Data)270................................................................................................................................................................
Appendix273................................................................................................................................................................
Appendix A Instruction Lists274................................................................................................................................................................
A.1 Symbols Used In Instruction Lists275................................................................................................................................................................
A.2 Instruction Lists277................................................................................................................................................................
Appendix B Instruction Maps286................................................................................................................................................................
B.1 Instruction Map287................................................................................................................................................................
B.2 "e" Format288................................................................................................................................................................
Index289................................................................................................................................................................

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