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Fujitsu FR Family Manuals
Manuals and User Guides for Fujitsu FR Family. We have
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Fujitsu FR Family manuals available for free PDF download: Instruction Manual
Fujitsu FR Family Instruction Manual (314 pages)
32-BIT MICROCONTROLLER
Brand:
Fujitsu
| Category:
Microcontrollers
| Size: 5.6 MB
Table of Contents
Table of Contents
9
Chapter 1 Fr Family Overview
25
Features of the FR Family CPU Core
26
Sample Configuration of an FR Family Device
27
Sample Configuration of the FR Family CPU
28
Chapter 2 Memory Architecture
29
FR Family Memory Space
30
Unused Vector Table Area
30
Direct Address Area
31
Vector Table Area
32
Contents of Vector Table Areas
33
Vector Table Area Initial Value
33
Bit Order and Byte Order
34
Word Alignment
35
Program Restrictions on Word Alignment
35
Data Restrictions on Word Alignment
35
Chapter 3 Register Descriptions
37
FR Family Register Configuration
38
General-Purpose Registers
39
Dedicated Registers
41
Program Counter (PC)
42
Program Status (PS)
43
Table Base Register (TBR)
47
Overview of the Table Base Register
47
Table Base Register Configuration
48
Table Base Register Functions
48
Precautions Related to the Table Base Register
48
Return Pointer (RP)
49
System Stack Pointer (SSP), User Stack Pointer (USP)
51
Multiplication/Division Register (MD)
53
Chapter 4 Reset and "Eit" Processing
55
Reset Processing
57
Basic Operations in "EIT" Processing
58
Vector Table Configuration
59
Interrupts
61
User Interrupts
62
Overview of User Interrupts
62
Conditions for Acceptance of User Interrupt Requests
62
How to Use User Interrupts
63
Non-Maskable Interrupts (NMI)
64
Exception Processing
66
Undefined Instruction Exceptions
67
Traps
68
INT" Instructions
69
INTE" Instruction
70
Step Trace Traps
71
Overview of Step Trace Traps
71
Conditions for Generation of Step Trace Traps
71
Step Trace Trap Operation
71
Pc" Values Saved for Step Trace Traps
71
Precautionary Information for Use of Step Trace Traps
71
Coprocessor Not Found Traps
72
Overview of Coprocessor Not Found Traps
72
Coprocessor Not Found Trap Operation
72
Pc" Values Saved for Coprocessor Not Present Traps
72
Coprocessor Error Trap
73
Coprocessor Error Trap Operation
73
Priority Levels
75
Chapter 5 Precautionary Information for the Fr Family Cpu
77
Pipeline Operation
78
Pipeline Operation and Interrupt Processing
79
Register Hazards
80
Delayed Branching Processing
82
Processing Non-Delayed Branching Instructions
84
Processing Delayed Branching Instructions
85
Chapter 6 Instruction Overview
87
Instruction Formats
88
Instruction Notation Formats
90
Chapter 7 Detailed Execution Instructions
91
Chapter 7 Detailed Execution Instructions
92
ADD (Add Word Data of Source Register to Destination Register)
96
ADD (Add 4-Bit Immediate Data to Destination Register)
97
ADD2 (Add 4-Bit Immediate Data to Destination Register)
98
ADDC (Add Word Data of Source Register and Carry Bit to Destination Register)
99
ADDN (Add Word Data of Source Register to Destination Register)
100
ADDN (Add Immediate Data to Destination Register)
101
ADDN2 (Add Immediate Data to Destination Register)
102
SUB (Subtract Word Data in Source Register from Destination Register)
103
SUBC (Subtract Word Data in Source Register and Carry Bit from Destination Register)
104
SUBN (Subtract Word Data in Source Register from Destination Register)
105
CMP (Compare Word Data in Source Register and Destination Register)
106
CMP (Compare Immediate Data of Source Register and Destination Register)
107
CMP2 (Compare Immediate Data and Destination Register)
108
AND (and Word Data of Source Register to Destination Register)
109
AND (and Word Data of Source Register to Data in Memory)
110
ANDH (and Half-Word Data of Source Register to Data in Memory)
112
ANDB (and Byte Data of Source Register to Data in Memory)
114
OR (or Word Data of Source Register to Destination Register)
116
OR (or Word Data of Source Register to Data in Memory)
117
ORH (or Half-Word Data of Source Register to Data in Memory)
119
ORB (or Byte Data of Source Register to Data in Memory)
121
EOR (Exclusive or Word Data of Source Register to Destination Register)
123
EOR (Exclusive or Word Data of Source Register to Data in Memory)
124
EORH (Exclusive or Half-Word Data of Source Register to Data in Memory)
126
EORB (Exclusive or Byte Data of Source Register to Data in Memory)
128
BANDL (and 4-Bit Immediate Data to Lower 4 Bits of Byte Data in Memory)
130
BANDH (and 4-Bit Immediate Data to Higher 4 Bits of Byte Data in Memory)
132
BORL (or 4-Bit Immediate Data to Lower 4 Bits of Byte Data in Memory)
134
BORH (or 4-Bit Immediate Data to Higher 4 Bits of Byte Data in Memory)
136
BEORL (Eor 4-Bit Immediate Data to Lower 4 Bits of Byte Data in Memory)
138
BEORH (Eor 4-Bit Immediate Data to Higher 4 Bits of Byte Data in Memory)
140
BTSTL (Test Lower 4 Bits of Byte Data in Memory)
142
BTSTH (Test Higher 4 Bits of Byte Data in Memory)
143
MUL (Multiply Word Data)
144
MULU (Multiply Unsigned Word Data)
146
MULH (Multiply Half-Word Data)
148
MULUH (Multiply Unsigned Half-Word Data)
150
DIV0S (Initial Setting up for Signed Division)
152
DIV0U (Initial Setting up for Unsigned Division)
154
DIV1 (Main Process of Division)
156
DIV2 (Correction When Remainder Is 0)
158
DIV3 (Correction When Remainder Is 0)
160
DIV4S (Correction Answer for Signed Division)
161
LSL (Logical Shift to the Left Direction)
162
LSL (Logical Shift to the Left Direction)
163
LSL2 (Logical Shift to the Left Direction)
164
LSR (Logical Shift to the Right Direction)
165
LSR (Logical Shift to the Right Direction)
166
LSR2 (Logical Shift to the Right Direction)
167
ASR (Arithmetic Shift to the Right Direction)
168
ASR (Arithmetic Shift to the Right Direction)
169
ASR2 (Arithmetic Shift to the Right Direction)
170
LDI:32 (Load Immediate 32-Bit Data to Destination Register)
171
LDI:20 (Load Immediate 20-Bit Data to Destination Register)
172
LDI:8 (Load Immediate 8-Bit Data to Destination Register)
173
LD (Load Word Data in Memory to Register)
174
LD (Load Word Data in Memory to Register)
175
LD (Load Word Data in Memory to Register)
176
LD (Load Word Data in Memory to Register)
177
LD (Load Word Data in Memory to Register)
178
LD (Load Word Data in Memory to Register)
179
LD (Load Word Data in Memory to Program Status Register)
181
LDUH (Load Half-Word Data in Memory to Register)
183
LDUH (Load Half-Word Data in Memory to Register)
184
LDUH (Load Half-Word Data in Memory to Register)
185
LDUB (Load Byte Data in Memory to Register)
186
LDUB (Load Byte Data in Memory to Register)
187
LDUB (Load Byte Data in Memory to Register)
188
ST (Store Word Data in Register to Memory)
189
ST (Store Word Data in Register to Memory)
190
ST (Store Word Data in Register to Memory)
191
ST (Store Word Data in Register to Memory)
192
ST (Store Word Data in Register to Memory)
193
ST (Store Word Data in Register to Memory)
194
ST (Store Word Data in Program Status Register to Memory)
195
STH (Store Half-Word Data in Register to Memory)
196
STH (Store Half-Word Data in Register to Memory)
197
STH (Store Half-Word Data in Register to Memory)
198
STB (Store Byte Data in Register to Memory)
199
STB (Store Byte Data in Register to Memory)
200
STB (Store Byte Data in Register to Memory)
201
MOV (Move Word Data in Source Register to Destination Register)
202
MOV (Move Word Data in Source Register to Destination Register)
203
MOV (Move Word Data in Program Status Register to Destination Register)
204
MOV (Move Word Data in Source Register to Destination Register)
205
MOV (Move Word Data in Source Register to Program Status Register)
206
JMP (Jump)
208
CALL (Call Subroutine)
209
CALL (Call Subroutine)
210
RET (Return from Subroutine)
211
INT (Software Interrupt)
212
INTE (Software Interrupt for Emulator)
214
RETI (Return from Interrupt)
216
Bcc (Branch Relative if Condition Satisfied)
218
JMP:D (Jump)
220
CALL:D (Call Subroutine)
221
CALL:D (Call Subroutine)
223
RET:D (Return from Subroutine)
225
Bcc:D (Branch Relative if Condition Satisfied)
227
DMOV (Move Word Data from Direct Address to Register)
229
DMOV (Move Word Data from Register to Direct Address)
230
DMOV (Move Word Data from Direct Address to Post Increment Register Indirect Address)
231
DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address)
233
DMOV (Move Word Data from Direct Address to Pre-Decrement Register Indirect Address)
235
DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address)
237
DMOVH (Move Half-Word Data from Direct Address to Register)
239
DMOVH (Move Half-Word Data from Register to Direct Address)
240
DMOVH (Move Half-Word Data from Direct Address to Post Increment Register Indirect Address)
241
DMOVH (Move Half-Word Data from Post Increment Register Indirect Address to Direct Address)
243
DMOVB (Move Byte Data from Direct Address to Register)
245
DMOVB (Move Byte Data from Register to Direct Address)
246
DMOVB (Move Byte Data from Direct Address to Post Increment Register Indirect Address)
247
DMOVB (Move Byte Data from Post Increment Register Indirect Address to Direct Address)
249
LDRES (Load Word Data in Memory to Resource)
251
STRES (Store Word Data in Resource to Memory)
252
COPOP (Coprocessor Operation)
253
COPLD (Load 32-Bit Data from Register to Coprocessor Register)
255
COPST (Store 32-Bit Data from Coprocessor Register to Register)
257
COPSV (Save 32-Bit Data from Coprocessor Register to Register)
259
NOP (no Operation)
261
ANDCCR (and Condition Code Register and Immediate Data)
262
ORCCR (or Condition Code Register and Immediate Data)
263
STILM (Set Immediate Data to Interrupt Level Mask Register)
264
ADDSP (Add Stack Pointer and Immediate Data)
265
EXTSB (Sign Extend from Byte Data to Word Data)
266
EXTUB (Unsign Extend from Byte Data to Word Data)
267
EXTSH (Sign Extend from Byte Data to Word Data)
268
EXTUH (Unsigned Extend from Byte Data to Word Data)
269
LDM0 (Load Multiple Registers)
270
LDM1 (Load Multiple Registers)
272
STM0 (Store Multiple Registers)
274
STM1 (Store Multiple Registers)
276
ENTER (Enter Function)
278
LEAVE (Leave Function)
280
XCHB (Exchange Byte Data)
282
Appendix
285
APPENDIX A Instruction Lists
286
Symbols Used in Instruction Lists
287
Instruction Lists
289
A.2 Instruction Lists
289
APPENDIX B Instruction Maps
298
Instruction Map
299
B.1 Instruction Map
299
E" Format
300
B.2 "E" Format
300
Index
301
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Fujitsu FR Family Instruction Manual (304 pages)
32-BIT MICROCONTROLLER
Brand:
Fujitsu
| Category:
Microcontrollers
| Size: 6.31 MB
Table of Contents
Table of Contents
9
Chapter 1 Fr Family Overview
17
Features of the FR Family CPU Core
18
Sample Configuration of an FR Family Device
19
Sample Configuration of the FR Family CPU
20
Chapter 2 Memory Architecture
21
FR Family Memory Space
22
Direct Address Area
23
Use of Operand Information Contained in Instructions
23
Vector Table Area
24
Bit Order and Byte Order
26
Word Alignment
27
Chapter 3 Register Descriptions
29
FR Family Register Configuration
30
General-Purpose Registers
31
Dedicated Registers
33
Program Counter (PC)
34
Program Status (PS)
35
Table Base Register (TBR)
39
Return Pointer (RP)
41
System Stack Pointer (SSP), User Stack Pointer (USP)
43
Multiplication/Division Register (MD)
45
Chapter 4 Reset and "Eit" Processing
47
Reset Processing
49
Basic Operations in "EIT" Processing
50
Interrupts
53
Overview of Interrupt Processing
53
External Interrupts
54
Overview of External Interrupts
54
Pc" Values Saved for Interrupts
55
Time to Start of Interrupt Processing
55
Non-Maskable Interrupts (NMI)
56
Overview of Non-Maskable Interrupts
56
Time to Start of Non-Maskable Interrupt Processing
56
How to Use Non-Maskable Interrupts
57
Pc" Values Saved for Non-Maskable Interrupts
57
Exception Processing
58
Undefined Instruction Exceptions
59
Undefined Instructions Placed in Delay Slots
59
Traps
60
INT" Instructions
61
Overview of the "Int" Instruction
61
Int" Instruction Operation
61
INTE" Instruction
62
Overview of the "Inte" Instruction
62
Step Trace Traps
63
Coprocessor Not Found Traps
64
Coprocessor Error Trap
65
Priority Levels
67
Chapter 5 Precautionary Information for the Fr Family Cpu
69
Pipeline Operation
70
Pipeline Operation and Interrupt Processing
71
Register Hazards
72
Delayed Branching Processing
74
Instructions Prohibited in Delay Slots
74
Processing Non-Delayed Branching Instructions
76
Processing Delayed Branching Instructions
77
Chapter 6 Instruction Overview
79
Instruction Formats
80
Instruction Notation Formats
82
Chapter 7 Detailed Execution Instructions
83
Chapter 7 Detailed Execution Instructions
84
ADD (Add Word Data of Source Register to Destination Register)
88
ADD (Add 4-Bit Immediate Data to Destination Register)
89
ADD2 (Add 4-Bit Immediate Data to Destination Register)
90
ADDC (Add Word Data of Source Register and Carry Bit to Destination Register)
91
ADDN (Add Word Data of Source Register to Destination Register)
92
ADDN (Add Immediate Data to Destination Register)
93
ADDN2 (Add Immediate Data to Destination Register)
94
SUB (Subtract Word Data in Source Register from Destination Register)
95
SUBC (Subtract Word Data in Source Register and Carry Bit from Destination Register)
96
SUBN (Subtract Word Data in Source Register from Destination Register)
97
CMP (Compare Word Data in Source Register and Destination Register)
98
CMP (Compare Immediate Data of Source Register and Destination Register)
99
CMP2 (Compare Immediate Data and Destination Register)
100
AND (and Word Data of Source Register to Destination Register)
101
AND (and Word Data of Source Register to Data in Memory)
102
ANDH (and Half-Word Data of Source Register to Data in Memory)
104
ANDB (and Byte Data of Source Register to Data in Memory)
106
OR (or Word Data of Source Register to Destination Register)
108
OR (or Word Data of Source Register to Data in Memory)
109
ORH (or Half-Word Data of Source Register to Data in Memory)
111
ORB (or Byte Data of Source Register to Data in Memory)
113
EOR (Exclusive or Word Data of Source Register to Destination Register)
115
EOR (Exclusive or Word Data of Source Register to Data in Memory)
116
EORH (Exclusive or Half-Word Data of Source Register to Data in Memory)
118
EORB (Exclusive or Byte Data of Source Register to Data in Memory)
120
BANDL (and 4-Bit Immediate Data to Lower 4 Bits of Byte Data in Memory)
122
BANDH (and 4-Bit Immediate Data to Higher 4 Bits of Byte Data in Memory)
124
BORL (or 4-Bit Immediate Data to Lower 4 Bits of Byte Data in Memory)
126
BORH (or 4-Bit Immediate Data to Higher 4 Bits of Byte Data in Memory)
128
BEORL (Eor 4-Bit Immediate Data to Lower 4 Bits of Byte Data in Memory)
130
BEORH (Eor 4-Bit Immediate Data to Higher 4 Bits of Byte Data in Memory)
132
BTSTL (Test Lower 4 Bits of Byte Data in Memory)
134
BTSTH (Test Higher 4 Bits of Byte Data in Memory)
135
MUL (Multiply Word Data)
136
MULU (Multiply Unsigned Word Data)
138
MULH (Multiply Half-Word Data)
140
MULUH (Multiply Unsigned Half-Word Data)
142
DIV0S (Initial Setting up for Signed Division)
144
DIV0U (Initial Setting up for Unsigned Division)
146
DIV1 (Main Process of Division)
148
DIV2 (Correction When Remainder Is 0)
150
DIV3 (Correction When Remainder Is 0)
152
DIV4S (Correction Answer for Signed Division)
153
LSL (Logical Shift to the Left Direction)
154
LSL (Logical Shift to the Left Direction)
155
LSL2 (Logical Shift to the Left Direction)
156
LSR (Logical Shift to the Right Direction)
157
LSR (Logical Shift to the Right Direction)
158
LSR2 (Logical Shift to the Right Direction)
159
ASR (Arithmetic Shift to the Right Direction)
160
ASR (Arithmetic Shift to the Right Direction)
161
ASR2 (Arithmetic Shift to the Right Direction)
162
LDI:32 (Load Immediate 32-Bit Data to Destination Register)
163
LDI:20 (Load Immediate 20-Bit Data to Destination Register)
164
LDI:8 (Load Immediate 8-Bit Data to Destination Register)
165
LD (Load Word Data in Memory to Register)
166
LD (Load Word Data in Memory to Register)
167
LD (Load Word Data in Memory to Register)
168
LD (Load Word Data in Memory to Register)
169
LD (Load Word Data in Memory to Register)
170
LD (Load Word Data in Memory to Register)
171
LD (Load Word Data in Memory to Program Status Register)
173
LDUH (Load Half-Word Data in Memory to Register)
175
LDUH (Load Half-Word Data in Memory to Register)
176
LDUH (Load Half-Word Data in Memory to Register)
177
LDUB (Load Byte Data in Memory to Register)
178
LDUB (Load Byte Data in Memory to Register)
179
LDUB (Load Byte Data in Memory to Register)
180
ST (Store Word Data in Register to Memory)
181
ST (Store Word Data in Register to Memory)
182
ST (Store Word Data in Register to Memory)
183
ST (Store Word Data in Register to Memory)
184
ST (Store Word Data in Register to Memory)
185
ST (Store Word Data in Register to Memory)
186
ST (Store Word Data in Program Status Register to Memory)
187
STH (Store Half-Word Data in Register to Memory)
188
STH (Store Half-Word Data in Register to Memory)
189
STH (Store Half-Word Data in Register to Memory)
190
STB (Store Byte Data in Register to Memory)
191
STB (Store Byte Data in Register to Memory)
192
STB (Store Byte Data in Register to Memory)
193
MOV (Move Word Data in Source Register to Destination Register)
194
MOV (Move Word Data in Source Register to Destination Register)
195
MOV (Move Word Data in Program Status Register to Destination Register)
196
MOV (Move Word Data in Source Register to Destination Register)
197
MOV (Move Word Data in Source Register to Program Status Register)
198
JMP (Jump)
199
CALL (Call Subroutine)
200
CALL (Call Subroutine)
201
RET (Return from Subroutine)
202
INT (Software Interrupt)
203
INTE (Software Interrupt for Emulator)
205
RETI (Return from Interrupt)
207
Bcc (Branch Relative if Condition Satisfied)
209
JMP:D (Jump)
211
CALL:D (Call Subroutine)
212
CALL:D (Call Subroutine)
214
RET:D (Return from Subroutine)
215
Bcc:D (Branch Relative if Condition Satisfied)
216
DMOV (Move Word Data from Direct Address to Register)
218
DMOV (Move Word Data from Register to Direct Address)
219
DMOV (Move Word Data from Direct Address to Post Increment Register Indirect Address)
220
DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address)
222
DMOV (Move Word Data from Direct Address to Pre-Decrement Register Indirect Address)
224
DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address)
226
DMOVH (Move Half-Word Data from Direct Address to Register)
228
DMOVH (Move Half-Word Data from Register to Direct Address)
229
DMOVH (Move Half-Word Data from Direct Address to Post Increment Register Indirect Address)
230
DMOVH (Move Half-Word Data from Post Increment Register Indirect Address to Direct Address)
232
DMOVB (Move Byte Data from Direct Address to Register)
234
DMOVB (Move Byte Data from Register to Direct Address)
235
DMOVB (Move Byte Data from Direct Address to Post Increment Register Indirect Address)
236
DMOVB (Move Byte Data from Post Increment Register Indirect Address to Direct Address)
238
LDRES (Load Word Data in Memory to Resource)
240
STRES (Store Word Data in Resource to Memory)
241
COPOP (Coprocessor Operation)
242
COPLD (Load 32-Bit Data from Register to Coprocessor Register)
244
COPST (Store 32-Bit Data from Coprocessor Register to Register)
246
COPSV (Save 32-Bit Data from Coprocessor Register to Register)
248
NOP (no Operation)
250
ANDCCR (and Condition Code Register and Immediate Data)
251
ORCCR (or Condition Code Register and Immediate Data)
252
STILM (Set Immediate Data to Interrupt Level Mask Register)
253
ADDSP (Add Stack Pointer and Immediate Data)
254
EXTSB (Sign Extend from Byte Data to Word Data)
255
EXTUB (Unsign Extend from Byte Data to Word Data)
256
EXTSH (Sign Extend from Byte Data to Word Data)
257
EXTUH (Unsigned Extend from Byte Data to Word Data)
258
LDM0 (Load Multiple Registers)
259
LDM1 (Load Multiple Registers)
261
STM0 (Store Multiple Registers)
263
STM1 (Store Multiple Registers)
265
ENTER (Enter Function)
267
LEAVE (Leave Function)
269
XCHB (Exchange Byte Data)
270
Appendix
273
APPENDIX A Instruction Lists
274
Symbols Used in Instruction Lists
275
Instruction Lists
277
A.2 Instruction Lists
277
APPENDIX B Instruction Maps
286
Instruction Map
287
B.1 Instruction Map
287
E" Format
288
B.2 "E" Format
288
Index
289
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