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CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER
6.3.3
Counter status register 0/1 (CSR0/1)
The register configuration of counter status register 0/1 (CSR0/1) is shown below.
I Counter status register 0/1 (CSR0/1)
The structure of counter status register 0/1 is shown below:
Address: 000063
000067
[Bit 7] CSTR: Count start bit
This bit controls the start and stop of UDCR counting.
CSTR
0
1
[Bit 6] CITE: Compare interrupt output control bit
This bit controls whether to enable or disable interrupt output to the CPU when a compare
detection flag (CMPF) is set (during a compare operation).
CITE
0
1
[Bit 5] UDIE: Overflow/underflow interrupt output control bit
This bit controls whether to enable or disable interrupt output to the CPU when OVFF/UDFF
is set (when overflow or underflow occurs).
UDIE
0
1
174
b i t
7
6
5
CSTR CITE
UDIE
H
H
R/W
R/W
R/W
Stops the counting operation (initial value)
Starts the counting operation
Disables compare interrupt output (initial value).
Enables compare interrupt output.
Disables overflow/underflow output (initial value).
Enables overflow/underflow output.
4
3
2
CMPF OVFF UDFF UDF1 UDF0
R/W
R/W
R/W
Operation
Compare interrupt output
Overflow/underflow interrupt output
1
0
Initial value
00000000
R
R
B
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