Control Status Register - Fujitsu FR60 Hardware Manual

8.2.1

Control Status Register

On the MB91F353A/351A/352A/353A, setting of data in the control status registers for
ch1, ch3, and ch5 is invalid.
■ Configurations of Control Status Registers
The configurations of the control status registers are shown below.
PCNH
Address : ch0 000126
PCNL
Address : ch0 000127
[Bit 15] CNTE (Timer Enable)
This bit enables operation of the 16-bit down counter.
Value
0
1
[Bit 14] STGR (Software Trigger)
Writing "1" into this bit applies software trigger.
The read value is always "0".
15 14
bit
CNTE STGR
H
ch1 00012E
R/W R/W
H
ch2 000136
H 0 0
ch3 00013E
H
ch4 000146
H
ch5 00014E
H
7 6
bit
EGS1 EGS0
H
ch1 00012F
R/W R/W
H
ch2 000137
H 0 0
ch3 00013E
H
X X
ch4 000147
H
ch5 00014F
H
Disabled (initial value)
Enabled
13 12 11
MDSE RTRG CKS1 CKS0
R/W R/W R/W
0 0 0
X X X
5 4 3
IREN IRQF IRS1 IRS0
R/W R/W R/W
0 0 0
X
Meaning
10 9 8
PGMS -
R/W R/W - <- Attribute
0 0 - <- Initial value
X -
<- Rewrite during
operation
2 1 0
- OSEL
R/W - R/W <- Attribute
0 X 0 <- Initial value
X - X
<- Rewrite during
operation
303