Dtp/Interrupt Enable Register (Enir); Fig. 16.5 Dtp/Interrupt Enable Register (Enir); Table 16-5 Function Of Each Bit Of Dtp/Interrupt Enable Register (Enir); Table 16-6 Correspondence Between Dtp/Interrupt Control Registers (Eirr And Enir) And Each Channel - Fujitsu MB90420/5 (A) Series Hardware Manual
F2mc-16lx family 16-bit microcontrollers
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16.4.2 DTP/Interrupt Enable Register (ENIR)
The DTP/Interrupt enable register (ENIR) enables/disables the output of interrupt request to CPU.
n DTP/Interrupt enable register (ENIR)
Address
bit 15
000030
EIRR
H
R/W : Both read and write
: Initial value
Table 16-5 Function of Each Bit of DTP/Interrupt Enable Register (ENIR)
Bit Name
bit 7
EN7 to EN0:
bit 6
External interrupt
bit 5
request enable
bit 4
bits
bit 6
bit 2
bit 1
bit 0
Table 16-6 Correspondence between DTP/Interrupt Control Registers (EIRR and ENIR)
DTP/External
Interrupt Pin
P03/INT7
P02/INT6
P01/INT5
P00/INT4
P53/INT3
P52/INT2
P51/INT1
P50/INT0
DTP/EXTERNAL INTERRUPT CIRCUIT
bit 8 bit 7 bit 6 bit 6 bit 4 bit 3 bit 2
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
R/W R/W R/W R/W R/W R/W R/W R/W
EN7 to
EN0
0
The external interrupt request is disabled.
1
The external interrupt request is enabled.
Fig. 16.5 DTP/Interrupt Enable Register (ENIR)
These bits enable/disable the output of interrupt requests to the CPU. When one of
these bits and one of ER7 to ER0 bits of the DTP/interrupt factor register (EIRR) that
correspond to that bit are 1, interrupt requests are output to the CPU.
Notes:
• When using the DTP/external interrupt pin, write 0 to the port direction register bit
corresponding to that pin to set the pin to input.
• The state of the DTP/external interrupt pin can be read directly using the port data
register irrespective of the state of the external interrupt request enable bit.
• The bits ER3 to ER0 of the DTP/interrupt factor register (EIRR) are set to 1
irrespective of the value of the external interrupt request enable bit when an interrupt
factor is detected.
and Each Channel
Interrupt
External Interrupt
Number
Request Flag Bit
#26 (1A
)
H
#26 (1A
)
H
#24 (18
)
H
#24 (18
)
H
#22 (16
)
H
#20 (14
)
H
#18 (12
)
H
#16 (10
)
H
bit 1 bit 0
External Interrupt Request Enable Bit
Function
External Interrupt
Request Enable Bit
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
16-9
Initial value
00000000
B
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
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