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CHAPTER 10 EXTERNAL INTERRUPT CONTROL BLOCK
10.2.1 Enable Interrupt Register (ENIRn)
The enable interrupt register (ENIRn) masks external interrupt request output.
I Enable interrupt register (ENIRn: ENable Interrupt Register n)
The register configuration of the enable interrupt register (ENIRn) is shown below.
ENI R 0
Ad d re ss :0 0 0 0C 9
H
ENI R1
Ad d re ss :0 0 0 0C B
H
The output of interrupt requests, corresponding to this register bit being set to 1, is enabled
(INT0 is enabled by EN0), and the request is output to the interrupt control register. The pins for
which the corresponding bit is set to 0 retain an interrupt source but do not issue an interrupt
request to the interrupt controller.
250
7
6
5
4
EN7
EN6
EN5
EN4
7
6
5
4
EN15 EN14 EN13 EN12 EN11 EN10
3
2
1
0
EN3
EN2
EN1
EN0
3
2
1
0
EN9
EN8
Initial value
00000000
[ R/W ]
Initial value
0000000 0
[ R/ W]
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