Figure 11.3-1 Block Diagram Of External Interrupt Circuit 2 Pins; Table 11.3-2 Correspondence Between Interrupt Enable Bits And External Interrupt Pins - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)
Block Diagram of External Interrupt Circuit 2 Pins

Figure 11.3-1 Block Diagram of External Interrupt Circuit 2 Pins

SPL: Pin state specification bit in the standby control register (STBC)
Tip:
The level at pins with a pull-up resistor option selected becomes "H" at a reset or in stop or
watch mode (SPL = 1).
Correspondence between Interrupt Enable Bits and External Interrupt Pins of External Interrupt
Circuit 2
Table 11.3-2 shows the correspondence between the interrupt enable bits and external interrupt
pins of external interrupt circuit 2.

Table 11.3-2 Correspondence between Interrupt Enable Bits and External Interrupt Pins

Register
EIE2
250
PDR (Port data register)
PDR read
PDR read (for bit manipulation instructions)
Output latch
PDR write
DDR
(Port data direction register)
DDR write
Stop or watch mode (SPL=1)
Bit name
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
To externel interrupt
(MB89120A only)
Stop or watch mode
(SPL=1)
External interrupt pin
IE20 INT20
IE21 INT21
IE22 INT22
IE23 INT23
IE24 INT24
IE25 INT25
IE26 INT26
IE27 INT27
Pull-up resistor
(optional)
Approx. 50 k /5.0 V
P-ch
P-ch
Pin
N-ch P00/INT20
P01/INT21
P02/INT22
P03/INT23
P04/INT24
P05/INT25
P06/INT26
P07/INT27