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CPU
15
PS
Source address
Fig. 2.5 Rule for Translating Real Addresses at General-purpose Register Area
HARDWARE CONFIGURATION
The 16 bits of the processor status (PS) can be divided into 8 upper bits
for a register bank pointer (RP) and 8 lower bits for a condition code register
(CCR). (See Fig. 2.4.)
14
13
12
11
10
RP
Vacant Vacant Vacant
RP
Fig. 2.4 Structure of Processor Status
The RP indicates the address of the current register bank. The relationship
between the contents of the RP and the real addresses is as shown in
Figure 2.5.
'0'
'0'
'0'
'0'
'0'
↓
↓
↓
↓
↓
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR has bits indicating the results of operations and transfer data
contents, and bits controlling the CPU operation when an interrupt occurs.
- H-flag
H-flag is set when a carry or a borrow out of bit 3 into bit 4
is generated as a result of operations; it is cleared in other
cases. This flag is used for decimal-correction instructions.
- I-flag
An interrupt is enabled when this flag is 1 and is disabled
when it is 0. The I-flag is 0 at reset.
- IL1 and IL0 These bits indicate the level of the currently-enabled
interrupt. The CPU executes interrupt processing only when
an interrupt with a value smaller than the value indicated by
this bit is requested.
IL1
0
0
1
1
- N-flag
The N-flag is set when the most significant bit is 1 as a result
of operations; it is cleared when the MSB is 0.
2– 7
9
8
7
6
5
H
I
IL1, 0
R P
'0'
'0'
'1'
R4 R3 R2 R1 R0
↓
↓
↓
↓
↓
↓
IL0
Interrupt level
0
1
1
0
2
1
3
4
3
2
1
0
N
Z
V
C
CCR
Lower bits of OP code
b2
b1
b0
↓
↓
↓
↓
↓
High and low
High
low = No interrupt
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