Dmac All-Channel Control Register (Dmacr); Table 2-4: Dmacr - Fujitsu FR Series Application Note

2.3.5 DMAC All-Channel Control Register (DMACR)

This register offers the master control for all five DMAC channels.
Bit
Name Explanation
No.
31 DMAE DMA Enable
30
... - -
29
28 PM01 Priority Mode
27
DMAH3
... ... DMA Halt
24 DMAH0
23
... - -
0
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DIRECT MEMORY ACCESS
Chapter 2 Direct Memory Access
Initial
Value
Value
0
0
1
x x
0
0
1
0,0,0,0
0
0,0,0,1
-
1,1,1,1
x x

Table 2-4: DMACR

- 13 -
Operation
DMAC transfer on all channels
disabled
DMAC transfer on all channels
enabled
-
Fixed priority (ch0 > ch1)
Alternating priority (ch1 > ch0)
DMAC operation on all channels
enabled
DMAC operation on all channels
temporarily stopped
-
MCU-AN-300059-E-V11