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3.11.1 Reset Source Register (RSRR) and Watchdog Cycle
Control Register (WTCR)
The reset source register (RSRR) is used to store the type of the generated reset. The
watchdog cycle control register (WTCR) is used to specify the cycle of the watchdog
timer.
I Reset source register (RSRR) and watchdog cycle control register (WTCR)
The reset source register (RSRR) and watchdog cycle control register (WTCR) are configured
as follows:
7
RSRR/WTCR
PONR
000480
( R )
H
[Bit 7]: PONR
If this bit is 1, the last reset was a power-on reset, and bits other than this bit are invalid.
[Bit 6]: (Reserved)
This bit is a reserved bit. Its value during read accesses is undefined.
[Bit 5]: WDOG
If this bit is 1, the last reset was a watchdog reset.
[Bit 4]: ERST
If this bit is 1, the last reset was caused by the external reset pin.
[Bit 3]: SRST
If this bit is 1, the last reset was caused by a software reset request.
[Bit 2]: (Reserved) LRST: not implemented on the MB91100 series
This bit is reserved. Its value during read accesses is undefined.
[Bits 1 and 0]: WT1 and WT0
These bits specify the watchdog cycle. The relationship between these bits and the cycle to
be selected is shown below. These bits are initialized by all resets.
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT
6
5
4
WDOG
ERST
(
)
( R )
( R )
3
2
1
SRST
WT1
( R )
(
)
( W )
Initial value after
0
power-on
WT0
1-XX X-00
B
( W )
69
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