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16.3.14
Receive complete register (RCR)
The reception complete register (RCR) indicates whether the reception of data to the
message buffer (x) completes. When an interrupt is enabled at completion of receiving,
an interrupt request is generated.
I Receive complete register (RCR)
7
6
5
R/W
R/W
R/W
R/W
: Read/Write
:
Reset value
Figure 16.3-22 Receive complete register (RCR)
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
bit0
RC0
bit1
RC1
bit2
RC2
bit3
RC3
bit4
RC4
bit5
RC5
bit6
RC6
bit7
RC7
Reset value
00000000
B
Reception complete bits0 (message buffer 0)
Not reception complete / Not receiving
0
1
Reception complete
Reception complete bits1 (message buffer 1)
Not reception complete / Not receiving
0
1
Reception complete
Reception complete bits2 (message buffer 2)
Not reception complete / Not receiving
0
1
Reception complete
Reception complete bits3 (message buffer 3)
Not reception complete / Not receiving
0
1
Reception complete
Reception complete bits4 (message buffer 4)
Not reception complete / Not receiving
0
1
Reception complete
Reception complete bits5 (message buffer 5)
Not reception complete / Not receiving
0
1
Reception complete
Reception complete bits6 (message buffer 6)
0
Not reception complete / Not receiving
1
Reception complete
Reception complete bits6 (message buffer 6)
Not reception complete / Not receiving
0
1
Reception complete
CHAPTER 16 CAN controller
515
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