Reception Complete Register (Rcr); Remote Request Receive Register (Rrtrr) - Fujitsu MB90420/5 (A) Series Hardware Manual

23.6.14 Reception Complete Register (RCR)

At completion of storing received message in the message buffer (x), RCx becomes 1.
If RIEx of the reception complete interrupt enable register is 1, an interrupt occurs.
n Reception complete register (RCR)
Address: 000049 (CAN0)
H
Address: 000079 (CAN1)
H
Read/write →
Initial value →
Address: 000048 (CAN0)
H
Address: 000078 (CAN1)
H
Read/write →
Initial value →
• Conditions for RCx = 0
Write 0 to RCx.
After processing the receive message, write 0 to RCx to set it to 0. Writing 1 to RCx is ignored.
1 is read when a read-modify-write instruction is perforrmed.
Note: If setting to 1 by completion of the receive operation and clearing by writing 0 occur at the same
time, the bit is set to 1.

23.6.15 Remote Request Receive Register (RRTRR)

When the received remote frame is stored in the message buffer (x), RRTRx is set to 1 (and RCx is set
simultaneously to 1).
n Remote request receive register (RRTRR)
Address: 00004B (CAN0)
H
Address: 00007B (CAN1)
H
Read/write →
Initial value →
Address: 00004A (CAN0)
H
Address: 00007A (CAN1)
H
Read/write →
Initial value →
• Conditions for RRTRx = 0
– Write 0 to RRTRx.
– After received data frame stored in message buffer (x) (at same time RCx set to 1)
– After completion of transmission from message buffer (x) (TCx of transmission complete register (TCR)
= 1)
Writing 1 to RRTRx is ignored.
1 is read when a read-modify-write instruction is performed.
Note: If setting to 1 and clearing by writing 0 occur at the same time, the bit is set to 1.
CAN CONTROLLER
15 14 13
RC15 RC14 RC13
(R/W) (R/W) (R/W)
(0) (0) (0)
7 6 5
RC7 RC6 RC5
(R/W) (R/W) (R/W)
(0) (0) (0)
15 14 13
RRTR15 RRTR14 RRTR13
(R/W) (R/W) (R/W)
(0) (0) (0)
7 6 5
RRTR7 RRTR6 RRTR5
(R/W) (R/W) (R/W)
(0) (0) (0)
23-23
12 11 10
RC12 RC11 RC10
(R/W) (R/W) (R/W)
(0) (0) (0)
4 3 2
RC4 RC3 RC2
(R/W) (R/W) (R/W)
(0) (0) (0)
12 11 10
RRTR12 RRTR11 RRTR10
(R/W) (R/W) (R/W)
(0) (0) (0)
4 3 2
RRTR4 RRTR3 RRTR2
(R/W) (R/W) (R/W)
(0) (0) (0)
← Bit No.
9 8
RC9 RC8
(R/W) (R/W)
(0) (0)
← Bit No.
1 0
RC1 RC0
(R/W) (R/W)
(0) (0)
← Bit No.
9 8
RRTR9 RRTR8
(R/W) (R/W)
(0) (0)
← Bit No.
1 0
RRTR1 RRTR0
(R/W) (R/W)
(0) (0)