Ppg0, 1 Output Pin Control Register (Ppgoe) - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

14.3.3 PPG0, 1 output pin control register (PPGOE)

PPG0,1 output control register
,
Address: ch0 1 0046H
Read/write
Initial value
This is an 8-bit control register that controls the pin output of this block.
[bits 7 to 5) PCS2 to 0 (PPG count select): Count clock selection bit
These bits select the channel 1 down counter operation clock as described below.
PCS2 PCS1
0
0
0
0
1
1
This bit is initialized to '000' upon a reset. This bit is readable and writable.
Note: In 8-bit prescaler + 8-bit PPG mode or in 16-bit PPG mode, ch1 PPG operates in
response to a counter clock from ch0. Therefore, the PCS1 bit is invalid.
[bits 4 to 2] PCM2 to 0 (PPG count mode): Count clock selection bit
These bits select the channel 0 down counter operation clock as described below.
PCM2 PCM1 PCM0
0 0
0 0
0 1
0 1
1 0
1 1
This bit is initialized to '000' upon a reset. This bit is readable and writable.
MB90580 Series
7 6
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0) (0)
Operation mode
PCS0
0 0 Peripheral clock (62.5-ns machine clock, 16 MHz)
0 1 Peripheral clock/2 (125-ns machine clock, 16 MHz)
1 0 Peripheral clock/4 (250-ns machine clock, 16 MHz)
1 1 Peripheral clock/8 (500-ms machine clock, 16 MHz)
0 0 Peripheral clock/16 (1-ms machine clock, 16 MHz)
1 1 Clock input from time base counter (128-ms, 4-Mhz source
Operation mode
0 Peripheral clock (62.5-ns machine clock, 16 MHz)
1 Peripheral clock/2 (125-ns machine clock, 16 MHz)
0 Peripheral clock/4 (250-ns machine clock, 16 MHz)
1 Peripheral clock/8 (500-ms machine clock, 16 MHz)
0 Peripheral clock/16 (1-ms machine clock, 16 MHz)
1 Clock input from time base counter (128-ms, 4-Mhz source
5
4 3 2
(0) (0) (0) (0)
14.3 Registers and Register Details
1 0 Bit No.
Reserved Reserved
PPGOE
(R/W) (R/W)
(0) (0)
Chapter 14: 8/16-Bit PPG 199